Commit 67bf6493 authored by Babu Moger's avatar Babu Moger Committed by Borislav Petkov
Browse files

x86/resctrl: Fix min_cbm_bits for AMD 



AMD systems support zero CBM (capacity bit mask) for cache allocation.
That is reflected in rdt_init_res_defs_amd() by:

  r->cache.arch_has_empty_bitmaps = true;

However given the unified code in cbm_validate(), checking for:

  val == 0 && !arch_has_empty_bitmaps

is not enough because of another check in cbm_validate():

  if ((zero_bit - first_bit) < r->cache.min_cbm_bits)

The default value of r->cache.min_cbm_bits = 1.

Leading to:

  $ cd /sys/fs/resctrl
  $ mkdir foo
  $ cd foo
  $ echo L3:0=0 > schemata
    -bash: echo: write error: Invalid argument
  $ cat /sys/fs/resctrl/info/last_cmd_status
    Need at least 1 bits in the mask

Initialize the min_cbm_bits to 0 for AMD. Also, remove the default
setting of min_cbm_bits and initialize it separately.

After the fix:

  $ cd /sys/fs/resctrl
  $ mkdir foo
  $ cd foo
  $ echo L3:0=0 > schemata
  $ cat /sys/fs/resctrl/info/last_cmd_status
    ok

Fixes: 316e7f90 ("x86/resctrl: Add struct rdt_cache::arch_has_{sparse, empty}_bitmaps")
Co-developed-by: default avatarStephane Eranian <eranian@google.com>
Signed-off-by: default avatarStephane Eranian <eranian@google.com>
Signed-off-by: default avatarBabu Moger <babu.moger@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarIngo Molnar <mingo@kernel.org>
Reviewed-by: default avatarJames Morse <james.morse@arm.com>
Reviewed-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Reviewed-by: default avatarFenghua Yu <fenghua.yu@intel.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/lkml/20220517001234.3137157-1-eranian@google.com
parent e7ad18d1

arch/x86/kernel/cpu/resctrl/core.c

+2 −6
Original line number Original line Diff line number Diff line
@@ -66,9 +66,6 @@ struct rdt_hw_resource rdt_resources_all[] = { 
			.rid			= RDT_RESOURCE_L3,

			.rid			= RDT_RESOURCE_L3,

			.name			= "L3",

			.name			= "L3",

			.cache_level		= 3,

			.cache_level		= 3,

			.cache = {

				.min_cbm_bits	= 1,

			},

			.domains		= domain_init(RDT_RESOURCE_L3),

			.domains		= domain_init(RDT_RESOURCE_L3),

			.parse_ctrlval		= parse_cbm,

			.parse_ctrlval		= parse_cbm,

			.format_str		= "%d=%0*x",

			.format_str		= "%d=%0*x",
@@ -83,9 +80,6 @@ struct rdt_hw_resource rdt_resources_all[] = { 
			.rid			= RDT_RESOURCE_L2,

			.rid			= RDT_RESOURCE_L2,

			.name			= "L2",

			.name			= "L2",

			.cache_level		= 2,

			.cache_level		= 2,

			.cache = {

				.min_cbm_bits	= 1,

			},

			.domains		= domain_init(RDT_RESOURCE_L2),

			.domains		= domain_init(RDT_RESOURCE_L2),

			.parse_ctrlval		= parse_cbm,

			.parse_ctrlval		= parse_cbm,

			.format_str		= "%d=%0*x",

			.format_str		= "%d=%0*x",
@@ -836,6 +830,7 @@ static __init void rdt_init_res_defs_intel(void) 
			r->cache.arch_has_sparse_bitmaps = false;

			r->cache.arch_has_sparse_bitmaps = false;

			r->cache.arch_has_empty_bitmaps = false;

			r->cache.arch_has_empty_bitmaps = false;

			r->cache.arch_has_per_cpu_cfg = false;

			r->cache.arch_has_per_cpu_cfg = false;

			r->cache.min_cbm_bits = 1;

		} else if (r->rid == RDT_RESOURCE_MBA) {

		} else if (r->rid == RDT_RESOURCE_MBA) {

			hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE;

			hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE;

			hw_res->msr_update = mba_wrmsr_intel;

			hw_res->msr_update = mba_wrmsr_intel;
@@ -856,6 +851,7 @@ static __init void rdt_init_res_defs_amd(void) 
			r->cache.arch_has_sparse_bitmaps = true;

			r->cache.arch_has_sparse_bitmaps = true;

			r->cache.arch_has_empty_bitmaps = true;

			r->cache.arch_has_empty_bitmaps = true;

			r->cache.arch_has_per_cpu_cfg = true;

			r->cache.arch_has_per_cpu_cfg = true;

			r->cache.min_cbm_bits = 0;

		} else if (r->rid == RDT_RESOURCE_MBA) {

		} else if (r->rid == RDT_RESOURCE_MBA) {

			hw_res->msr_base = MSR_IA32_MBA_BW_BASE;

			hw_res->msr_base = MSR_IA32_MBA_BW_BASE;

			hw_res->msr_update = mba_wrmsr_amd;

			hw_res->msr_update = mba_wrmsr_amd;