Commit 67abcd0c authored by Jiaran Zhang's avatar Jiaran Zhang Committed by Zheng Zengkai
Browse files

net: hns3: add support for imp-handle ras capability 

mainline inclusion
from mainline-master
commit e65e9f5c
category: feature
bugzilla: 173966
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e65e9f5c2e4efc17657d016d767eb7010d9dd598



----------------------------------------------------------------------

IMP(Intelligent Management Processor) firmware add a new feature to
handle and consolidate RAS information for new devices, NIC driver
only needs to query the reported RAS information. NIC driver adds
support for this feature.

Driver queries device capability to check whether IMP support this
feature, If yes, execute the new RAS processing branch.

In order to add a method to check whether PF supports imp-handle RAS
feature, add dumping this info in debugfs.

Signed-off-by: default avatarJiaran Zhang <zhangjiaran@huawei.com>
Signed-off-by: default avatarGuangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Reviewed-by: default avatarYongxin Li <liyongxin1@huawei.com>
Signed-off-by: default avatarJunxin Chen <chenjunxin1@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent ce991842

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+4 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ enum HNAE3_DEV_CAP_BITS { 
	HNAE3_DEV_SUPPORT_STASH_B,

	HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,

	HNAE3_DEV_SUPPORT_PAUSE_B,

	HNAE3_DEV_SUPPORT_RAS_IMP_B,

	HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,

	HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,

	HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
@@ -128,6 +129,9 @@ enum HNAE3_DEV_CAP_BITS { 
#define hnae3_dev_phy_imp_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)



#define hnae3_dev_ras_imp_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps)



#define hnae3_dev_tqp_txrx_indep_supported(hdev) \

	test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

+3 −0
Original line number Diff line number Diff line
@@ -349,6 +349,9 @@ static struct hns3_dbg_cap_info hns3_dbg_cap[] = { 
	}, {

		.name = "support imp-controlled PHY",

		.cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B,

	}, {

		.name = "support imp-controlled RAS",

		.cap_bit = HNAE3_DEV_SUPPORT_RAS_IMP_B,

	}, {

		.name = "support rxd advanced layout",

		.cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c

+2 −0
Original line number Diff line number Diff line
@@ -387,6 +387,8 @@ static void hclge_parse_capability(struct hclge_dev *hdev, 
		set_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps);

	if (hnae3_get_bit(caps, HCLGE_CAP_PHY_IMP_B))

		set_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, ae_dev->caps);

	if (hnae3_get_bit(caps, HCLGE_CAP_RAS_IMP_B))

		set_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, ae_dev->caps);

	if (hnae3_get_bit(caps, HCLGE_CAP_RXD_ADV_LAYOUT_B))

		set_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, ae_dev->caps);

	if (hnae3_get_bit(caps, HCLGE_CAP_PORT_VLAN_BYPASS_B)) {

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+1 −0
Original line number Diff line number Diff line
@@ -392,6 +392,7 @@ enum HCLGE_CAP_BITS { 
	HCLGE_CAP_HW_PAD_B,

	HCLGE_CAP_STASH_B,

	HCLGE_CAP_UDP_TUNNEL_CSUM_B,

	HCLGE_CAP_RAS_IMP_B = 12,

	HCLGE_CAP_FEC_B = 13,

	HCLGE_CAP_PAUSE_B = 14,

	HCLGE_CAP_RXD_ADV_LAYOUT_B = 15,

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+1 −1
Original line number Diff line number Diff line
@@ -4299,7 +4299,7 @@ static void hclge_errhand_service_task(struct hclge_dev *hdev) 
	if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))

		return;



	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)

	if (hnae3_dev_ras_imp_supported(hdev))

		hclge_handle_err_recovery(hdev);

	else

		hclge_misc_err_recovery(hdev);