dt-bindings: clock: renesas: Document RZ/V2L SoC

$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode

title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode

maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>

description: |

  On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module

  On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module

  Standby Mode share the same register block.

  They provide the following functionalities:

properties:

  compatible:

    const: renesas,r9a07g044-cpg  # RZ/G2{L,LC}

    enum:

      - renesas,r9a07g044-cpg  # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg  # RZ/V2L

  reg:

    maxItems: 1

    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/r9a07g044-cpg.h>

        <dt-bindings/clock/r9a07g*-cpg.h>

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.

        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.

    const: 2

  '#power-domain-cells':

  '#reset-cells':

    description:

      The single reset specifier cell must be the module number, as defined in

      the <dt-bindings/clock/r9a07g044-cpg.h>.

      the <dt-bindings/clock/r9a07g0*-cpg.h>.

    const: 1

required: