Commit 67804e48 authored by John Harrison's avatar John Harrison
Browse files

drm/i915/gt: Start adding module oriented dmesg output 



When trying to analyse bug reports from CI, customers, etc. it can be
difficult to work out exactly what is happening on which GT in a
multi-GT system. So add GT oriented debug/error message wrappers. If
used instead of the drm_ equivalents, you get the same output but with
a GT# prefix on it.

v2: Go back to using lower case names (combined review feedback).
Convert intel_gt.c as a first step.
v3: Add gt_err_ratelimited() as well, undo one conversation that might
not have a GT pointer in some scenarios (review feedback from Michal W).
Split definitions into separate header (review feedback from Jani).
Convert all intel_gt*.c files.
v4: Re-order some macro definitions (Andi S), update (c) date (Tvrtko)

Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230111200429.2139084-2-John.C.Harrison@Intel.com
parent 0c8a6e9e

drivers/gpu/drm/i915/gt/intel_gt.c

+46 −50
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include "intel_gt_debugfs.h"

#include "intel_gt_mcr.h"

#include "intel_gt_pm.h"

#include "intel_gt_print.h"

#include "intel_gt_regs.h"

#include "intel_gt_requests.h"

#include "intel_migrate.h"
@@ -89,8 +90,7 @@ static int intel_gt_probe_lmem(struct intel_gt *gt) 
		if (err == -ENODEV)

			return 0;



		drm_err(&i915->drm,

			"Failed to setup region(%d) type=%d\n",

		gt_err(gt, "Failed to setup region(%d) type=%d\n",

		       err, INTEL_MEMORY_LOCAL);

		return err;

	}
@@ -200,14 +200,14 @@ int intel_gt_init_hw(struct intel_gt *gt) 


	ret = i915_ppgtt_init_hw(gt);

	if (ret) {

		drm_err(&i915->drm, "Enabling PPGTT failed (%d)\n", ret);

		gt_err(gt, "Enabling PPGTT failed (%d)\n", ret);

		goto out;

	}



	/* We can't enable contexts until all firmware is loaded */

	ret = intel_uc_init_hw(&gt->uc);

	if (ret) {

		i915_probe_error(i915, "Enabling uc failed (%d)\n", ret);

		gt_probe_error(gt, "Enabling uc failed (%d)\n", ret);

		goto out;

	}
@@ -257,7 +257,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt, 
		 * some errors might have become stuck,

		 * mask them.

		 */

		drm_dbg(&gt->i915->drm, "EIR stuck: 0x%08x, masking\n", eir);

		gt_dbg(gt, "EIR stuck: 0x%08x, masking\n", eir);

		intel_uncore_rmw(uncore, EMR, 0, eir);

		intel_uncore_write(uncore, GEN2_IIR,

				   I915_MASTER_ERROR_INTERRUPT);
@@ -291,7 +291,7 @@ static void gen6_check_faults(struct intel_gt *gt) 
	for_each_engine(engine, gt, id) {

		fault = GEN6_RING_FAULT_REG_READ(engine);

		if (fault & RING_FAULT_VALID) {

			drm_dbg(&engine->i915->drm, "Unexpected fault\n"

			gt_dbg(gt, "Unexpected fault\n"

			       "\tAddr: 0x%08lx\n"

			       "\tAddress space: %s\n"

			       "\tSource ID: %d\n"
@@ -327,7 +327,7 @@ static void xehp_check_faults(struct intel_gt *gt) 
		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |

			     ((u64)fault_data0 << 12);



		drm_dbg(&gt->i915->drm, "Unexpected fault\n"

		gt_dbg(gt, "Unexpected fault\n"

		       "\tAddr: 0x%08x_%08x\n"

		       "\tAddress space: %s\n"

		       "\tEngine ID: %d\n"
@@ -368,7 +368,7 @@ static void gen8_check_faults(struct intel_gt *gt) 
		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |

			     ((u64)fault_data0 << 12);



		drm_dbg(&uncore->i915->drm, "Unexpected fault\n"

		gt_dbg(gt, "Unexpected fault\n"

		       "\tAddr: 0x%08x_%08x\n"

		       "\tAddress space: %s\n"

		       "\tEngine ID: %d\n"
@@ -472,7 +472,7 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size) 
	if (IS_ERR(obj))

		obj = i915_gem_object_create_internal(i915, size);

	if (IS_ERR(obj)) {

		drm_err(&i915->drm, "Failed to allocate scratch page\n");

		gt_err(gt, "Failed to allocate scratch page\n");

		return PTR_ERR(obj);

	}
@@ -727,8 +727,7 @@ int intel_gt_init(struct intel_gt *gt) 


	err = intel_gt_init_hwconfig(gt);

	if (err)

		drm_err(&gt->i915->drm, "Failed to retrieve hwconfig table: %pe\n",

			ERR_PTR(err));

		gt_err(gt, "Failed to retrieve hwconfig table: %pe\n", ERR_PTR(err));



	err = __engines_record_defaults(gt);

	if (err)
@@ -885,7 +884,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915) 
	gt->name = "Primary GT";

	gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;



	drm_dbg(&i915->drm, "Setting up %s\n", gt->name);

	gt_dbg(gt, "Setting up %s\n", gt->name);

	ret = intel_gt_tile_setup(gt, phys_addr);

	if (ret)

		return ret;
@@ -910,7 +909,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915) 
		gt->info.engine_mask = gtdef->engine_mask;

		gt->info.id = i;



		drm_dbg(&i915->drm, "Setting up %s\n", gt->name);

		gt_dbg(gt, "Setting up %s\n", gt->name);

		if (GEM_WARN_ON(range_overflows_t(resource_size_t,

						  gtdef->mapping_base,

						  SZ_16M,
@@ -998,8 +997,7 @@ get_reg_and_bit(const struct intel_engine_cs *engine, const bool gen8, 
	const unsigned int class = engine->class;

	struct reg_and_bit rb = { };



	if (drm_WARN_ON_ONCE(&engine->i915->drm,

			     class >= num || !regs[class].reg))

	if (gt_WARN_ON_ONCE(engine->gt, class >= num || !regs[class].reg))

		return rb;



	rb.reg = regs[class];
@@ -1096,8 +1094,7 @@ static void mmio_invalidate_full(struct intel_gt *gt) 
		return;

	}



	if (drm_WARN_ONCE(&i915->drm, !num,

			  "Platform does not implement TLB invalidation!"))

	if (gt_WARN_ONCE(gt, !num, "Platform does not implement TLB invalidation!"))

		return;



	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
@@ -1162,8 +1159,7 @@ static void mmio_invalidate_full(struct intel_gt *gt) 
		}



		if (wait_for_invalidate(gt, rb))

			drm_err_ratelimited(&gt->i915->drm,

					    "%s TLB invalidation did not complete in %ums!\n",

			gt_err_ratelimited(gt, "%s TLB invalidation did not complete in %ums!\n",

					   engine->name, TLB_INVAL_TIMEOUT_MS);

	}

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

+4 −4
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include "i915_reg.h"

#include "intel_gt.h"

#include "intel_gt_clock_utils.h"

#include "intel_gt_print.h"

#include "intel_gt_regs.h"



static u32 read_reference_ts_freq(struct intel_uncore *uncore)
@@ -193,8 +194,7 @@ void intel_gt_init_clock_frequency(struct intel_gt *gt) 
void intel_gt_check_clock_frequency(const struct intel_gt *gt)

{

	if (gt->clock_frequency != read_clock_frequency(gt->uncore)) {

		dev_err(gt->i915->drm.dev,

			"GT clock frequency changed, was %uHz, now %uHz!\n",

		gt_err(gt, "GT clock frequency changed, was %uHz, now %uHz!\n",

		       gt->clock_frequency,

		       read_clock_frequency(gt->uncore));

	}

drivers/gpu/drm/i915/gt/intel_gt_irq.c

+4 −5
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include "intel_breadcrumbs.h"

#include "intel_gt.h"

#include "intel_gt_irq.h"

#include "intel_gt_print.h"

#include "intel_gt_regs.h"

#include "intel_uncore.h"

#include "intel_rps.h"
@@ -47,8 +48,7 @@ gen11_gt_engine_identity(struct intel_gt *gt, 
		 !time_after32(local_clock() >> 10, timeout_ts));



	if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {

		drm_err(&gt->i915->drm,

			"INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",

		gt_err(gt, "INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",

		       bank, bit, ident);

		return 0;

	}
@@ -378,8 +378,7 @@ void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) 
	if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |

		      GT_BSD_CS_ERROR_INTERRUPT |

		      GT_CS_MASTER_ERROR_INTERRUPT))

		drm_dbg(&gt->i915->drm, "Command parser error, gt_iir 0x%08x\n",

			gt_iir);

		gt_dbg(gt, "Command parser error, gt_iir 0x%08x\n", gt_iir);



	if (gt_iir & GT_PARITY_ERROR(gt->i915))

		gen7_parity_error_irq_handler(gt, gt_iir);

drivers/gpu/drm/i915/gt/intel_gt_mcr.c

+4 −5
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include "i915_drv.h"



#include "intel_gt_mcr.h"

#include "intel_gt_print.h"

#include "intel_gt_regs.h"



/**
@@ -158,7 +159,7 @@ void intel_gt_mcr_init(struct intel_gt *gt) 
			 GEN12_MEML3_EN_MASK);



		if (!gt->info.mslice_mask) /* should be impossible! */

			drm_warn(&i915->drm, "mslice mask all zero!\n");

			gt_warn(gt, "mslice mask all zero!\n");

	}



	if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
@@ -205,7 +206,7 @@ void intel_gt_mcr_init(struct intel_gt *gt) 
			~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &

			GEN10_L3BANK_MASK;

		if (!gt->info.l3bank_mask) /* should be impossible! */

			drm_warn(&i915->drm, "L3 bank mask is all zero!\n");

			gt_warn(gt, "L3 bank mask is all zero!\n");

	} else if (GRAPHICS_VER(i915) >= 11) {

		/*

		 * We expect all modern platforms to have at least some
@@ -394,9 +395,7 @@ void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags) 
	 * releasing it properly.

	 */

	if (err == -ETIMEDOUT) {

		drm_err_ratelimited(&gt->i915->drm,

				    "GT%u hardware MCR steering semaphore timed out",

				    gt->info.id);

		gt_err_ratelimited(gt, "hardware MCR steering semaphore timed out");

		add_taint_for_CI(gt->i915, TAINT_WARN);  /* CI is now unreliable */

	}

}

drivers/gpu/drm/i915/gt/intel_gt_pm.c

+4 −5
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include "intel_gt.h"

#include "intel_gt_clock_utils.h"

#include "intel_gt_pm.h"

#include "intel_gt_print.h"

#include "intel_gt_requests.h"

#include "intel_llc.h"

#include "intel_pm.h"
@@ -275,8 +276,7 @@ int intel_gt_resume(struct intel_gt *gt) 
	/* Only when the HW is re-initialised, can we replay the requests */

	err = intel_gt_init_hw(gt);

	if (err) {

		i915_probe_error(gt->i915,

				 "Failed to initialize GPU, declaring it wedged!\n");

		gt_probe_error(gt, "Failed to initialize GPU, declaring it wedged!\n");

		goto err_wedged;

	}
@@ -293,8 +293,7 @@ int intel_gt_resume(struct intel_gt *gt) 


		intel_engine_pm_put(engine);

		if (err) {

			drm_err(&gt->i915->drm,

				"Failed to restart %s (%d)\n",

			gt_err(gt, "Failed to restart %s (%d)\n",

			       engine->name, err);

			goto err_wedged;

		}