Commit 67322d13 authored by Nick Forrington's avatar Nick Forrington Committed by Arnaldo Carvalho de Melo
Browse files

perf vendors events arm64: Update Cortex A57/A72 

Categorise and add missing PMU events for Cortex-A57/A72, based on:
https://github.com/ARM-software/data/blob/master/pmu/cortex-a57.json
https://github.com/ARM-software/data/blob/master/pmu/cortex-a72.json



These contain the same events, and are based on the Arm Technical
Reference Manuals for Cortex-A57 and Cortex-A72.

Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Signed-off-by: default avatarNick Forrington <nick.forrington@arm.com>
Acked-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Andrew Kilroy <andrew.kilroy@arm.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20220517135805.313184-2-nick.forrington@arm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 2531169e

tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/branch.json

0 → 100644
+17 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "BR_MIS_PRED"

    },

    {

        "ArchStdEvent": "BR_PRED"

    },

    {

        "ArchStdEvent": "BR_IMMED_SPEC"

    },

    {

        "ArchStdEvent": "BR_RETURN_SPEC"

    },

    {

        "ArchStdEvent": "BR_INDIRECT_SPEC"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/bus.json

0 → 100644
+29 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "CPU_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS"

    },

    {

        "ArchStdEvent": "BUS_CYCLES"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_WR"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_SHARED"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_NOT_SHARED"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_NORMAL"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_PERIPH"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json→tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/cache.json

+80 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "L1D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L1D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_RD"

    },

    {

        "ArchStdEvent": "L1D_TLB_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "L2D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "L2D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_RD"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_WR"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_SHARED"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_NOT_SHARED"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_NORMAL"

    },

    {

        "ArchStdEvent": "BUS_ACCESS_PERIPH"

    },

    {

        "ArchStdEvent": "MEM_ACCESS_RD"

    },

    {

        "ArchStdEvent": "MEM_ACCESS_WR"

    },

    {

        "ArchStdEvent": "UNALIGNED_LD_SPEC"

    },

    {

        "ArchStdEvent": "UNALIGNED_ST_SPEC"

    },

    {

        "ArchStdEvent": "UNALIGNED_LDST_SPEC"

    },

    {

        "ArchStdEvent": "LDREX_SPEC"

    },

    {

        "ArchStdEvent": "STREX_PASS_SPEC"

    },

    {

        "ArchStdEvent": "STREX_FAIL_SPEC"

        "ArchStdEvent": "L1I_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "LD_SPEC"

        "ArchStdEvent": "L1I_TLB_REFILL"

    },

    {

        "ArchStdEvent": "ST_SPEC"

        "ArchStdEvent": "L1D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "LDST_SPEC"

        "ArchStdEvent": "L1D_CACHE"

    },

    {

        "ArchStdEvent": "DP_SPEC"

        "ArchStdEvent": "L1D_TLB_REFILL"

    },

    {

        "ArchStdEvent": "ASE_SPEC"

        "ArchStdEvent": "L1I_CACHE"

    },

    {

        "ArchStdEvent": "VFP_SPEC"

        "ArchStdEvent": "L1D_CACHE_WB"

    },

    {

        "ArchStdEvent": "PC_WRITE_SPEC"

        "ArchStdEvent": "L2D_CACHE"

    },

    {

        "ArchStdEvent": "CRYPTO_SPEC"

        "ArchStdEvent": "L2D_CACHE_REFILL"

    },

    {

        "ArchStdEvent": "BR_IMMED_SPEC"

        "ArchStdEvent": "L2D_CACHE_WB"

    },

    {

        "ArchStdEvent": "BR_RETURN_SPEC"

    },

    {

        "ArchStdEvent": "BR_INDIRECT_SPEC"

    },

    {

        "ArchStdEvent": "ISB_SPEC"

    },

    {

        "ArchStdEvent": "DSB_SPEC"

    },

    {

        "ArchStdEvent": "DMB_SPEC"

        "ArchStdEvent": "L1D_CACHE_RD"

    },

    {

        "ArchStdEvent": "EXC_UNDEF"

        "ArchStdEvent": "L1D_CACHE_WR"

    },

    {

        "ArchStdEvent": "EXC_SVC"

        "ArchStdEvent": "L1D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "EXC_PABORT"

        "ArchStdEvent": "L1D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "EXC_DABORT"

        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "EXC_IRQ"

        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "EXC_FIQ"

        "ArchStdEvent": "L1D_CACHE_INVAL"

    },

    {

        "ArchStdEvent": "EXC_SMC"

        "ArchStdEvent": "L1D_TLB_REFILL_RD"

    },

    {

        "ArchStdEvent": "EXC_HVC"

        "ArchStdEvent": "L1D_TLB_REFILL_WR"

    },

    {

        "ArchStdEvent": "EXC_TRAP_PABORT"

        "ArchStdEvent": "L2D_CACHE_RD"

    },

    {

        "ArchStdEvent": "EXC_TRAP_DABORT"

        "ArchStdEvent": "L2D_CACHE_WR"

    },

    {

        "ArchStdEvent": "EXC_TRAP_OTHER"

        "ArchStdEvent": "L2D_CACHE_REFILL_RD"

    },

    {

        "ArchStdEvent": "EXC_TRAP_IRQ"

        "ArchStdEvent": "L2D_CACHE_REFILL_WR"

    },

    {

        "ArchStdEvent": "EXC_TRAP_FIQ"

        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"

    },

    {

        "ArchStdEvent": "RC_LD_SPEC"

        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"

    },

    {

        "ArchStdEvent": "RC_ST_SPEC"

        "ArchStdEvent": "L2D_CACHE_INVAL"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/exception.json

0 → 100644
+47 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "EXC_TAKEN"

    },

    {

        "ArchStdEvent": "MEMORY_ERROR"

    },

    {

        "ArchStdEvent": "EXC_UNDEF"

    },

    {

        "ArchStdEvent": "EXC_SVC"

    },

    {

        "ArchStdEvent": "EXC_PABORT"

    },

    {

        "ArchStdEvent": "EXC_DABORT"

    },

    {

        "ArchStdEvent": "EXC_IRQ"

    },

    {

        "ArchStdEvent": "EXC_FIQ"

    },

    {

        "ArchStdEvent": "EXC_SMC"

    },

    {

        "ArchStdEvent": "EXC_HVC"

    },

    {

        "ArchStdEvent": "EXC_TRAP_PABORT"

    },

    {

        "ArchStdEvent": "EXC_TRAP_DABORT"

    },

    {

        "ArchStdEvent": "EXC_TRAP_OTHER"

    },

    {

        "ArchStdEvent": "EXC_TRAP_IRQ"

    },

    {

        "ArchStdEvent": "EXC_TRAP_FIQ"

    }

]

tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/instruction.json

0 → 100644
+68 −0
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "SW_INCR"

    },

    {

        "ArchStdEvent": "INST_RETIRED"

    },

    {

        "ArchStdEvent": "EXC_RETURN"

    },

    {

        "ArchStdEvent": "CID_WRITE_RETIRED"

    },

    {

        "ArchStdEvent": "INST_SPEC"

    },

    {

        "ArchStdEvent": "TTBR_WRITE_RETIRED"

    },

    {

        "ArchStdEvent": "LDREX_SPEC"

    },

    {

        "ArchStdEvent": "STREX_PASS_SPEC"

    },

    {

        "ArchStdEvent": "STREX_FAIL_SPEC"

    },

    {

        "ArchStdEvent": "LD_SPEC"

    },

    {

        "ArchStdEvent": "ST_SPEC"

    },

    {

        "ArchStdEvent": "LDST_SPEC"

    },

    {

        "ArchStdEvent": "DP_SPEC"

    },

    {

        "ArchStdEvent": "ASE_SPEC"

    },

    {

        "ArchStdEvent": "VFP_SPEC"

    },

    {

        "ArchStdEvent": "PC_WRITE_SPEC"

    },

    {

        "ArchStdEvent": "CRYPTO_SPEC"

    },

    {

        "ArchStdEvent": "ISB_SPEC"

    },

    {

        "ArchStdEvent": "DSB_SPEC"

    },

    {

        "ArchStdEvent": "DMB_SPEC"

    },

    {

        "ArchStdEvent": "RC_LD_SPEC"

    },

    {

        "ArchStdEvent": "RC_ST_SPEC"

    }

]