Commit 67245a7e authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Haswell v33 events 



Updates descriptions and encodings. Adds BR_MISP_EXEC.INDIRECT events.

Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Samantha Alt <samantha.alt@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 74a87b6a

tools/perf/pmu-events/arch/x86/haswell/cache.json

+19 −19
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",

        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",

        "CounterMask": "1",

        "EventCode": "0x48",

        "EventName": "L1D_PEND_MISS.FB_FULL",

tools/perf/pmu-events/arch/x86/haswell/pipeline.json

+8 −0
Original line number Diff line number Diff line
@@ -194,6 +194,14 @@ 
        "SampleAfterValue": "200003",

        "UMask": "0xc4"

    },

    {

        "BriefDescription": "Speculative mispredicted indirect branches",

        "EventCode": "0x89",

        "EventName": "BR_MISP_EXEC.INDIRECT",

        "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).",

        "SampleAfterValue": "200003",

        "UMask": "0xe4"

    },

    {

        "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.",

        "EventCode": "0x89",

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ GenuineIntel-6-9[6C],v1.03,elkhartlake,core 
GenuineIntel-6-5[CF],v13,goldmont,core

GenuineIntel-6-7A,v1.01,goldmontplus,core

GenuineIntel-6-A[DE],v1.01,graniterapids,core

GenuineIntel-6-(3C|45|46),v32,haswell,core

GenuineIntel-6-(3C|45|46),v33,haswell,core

GenuineIntel-6-3F,v26,haswellx,core

GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core

GenuineIntel-6-6[AC],v1.19,icelakex,core

tools/perf/pmu-events/arch/x86/haswell/memory.json

+19 −19

File changed.

Contains only whitespace changes.