Commit 6705b58d authored by Quentin Schulz's avatar Quentin Schulz Committed by David S. Miller
Browse files

net: phy: mscc: remove the TR CLK disable magic value 



This patch adds a define for the 0x8000 magic value used to perform
enable/disable actions on the "token ring clock". The patch is only
cosmetic.

Signed-off-by: default avatarQuentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: default avatarAntoine Tenart <antoine.tenart@bootlin.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c7cd2a6a

drivers/net/phy/mscc/mscc.h

+1 −0
Original line number Diff line number Diff line
@@ -252,6 +252,7 @@ enum rgmii_clock_delay { 
/* Test page Registers */

#define MSCC_PHY_TEST_PAGE_5		  5

#define MSCC_PHY_TEST_PAGE_8		  8

#define TR_CLK_DISABLE			  0x8000

#define MSCC_PHY_TEST_PAGE_9		  9

#define MSCC_PHY_TEST_PAGE_20		  20

#define MSCC_PHY_TEST_PAGE_24		  24

drivers/net/phy/mscc/mscc_main.c

+5 −5
Original line number Diff line number Diff line
@@ -629,7 +629,7 @@ static int vsc8531_pre_init_seq_set(struct phy_device *phydev) 
	if (rc < 0)

		return rc;

	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,

			      MSCC_PHY_TEST_PAGE_8, 0x8000, 0x8000);

			      MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE);

	if (rc < 0)

		return rc;
@@ -1026,7 +1026,7 @@ static int vsc8574_config_pre_init(struct phy_device *phydev) 
	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);



	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);

	reg |= 0x8000;

	reg |= TR_CLK_DISABLE;

	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);



	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
@@ -1046,7 +1046,7 @@ static int vsc8574_config_pre_init(struct phy_device *phydev) 
	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);



	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);

	reg &= ~0x8000;

	reg &= ~TR_CLK_DISABLE;

	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);



	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
@@ -1196,7 +1196,7 @@ static int vsc8584_config_pre_init(struct phy_device *phydev) 
	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);



	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);

	reg |= 0x8000;

	reg |= TR_CLK_DISABLE;

	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);



	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
@@ -1225,7 +1225,7 @@ static int vsc8584_config_pre_init(struct phy_device *phydev) 
	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);



	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);

	reg &= ~0x8000;

	reg &= ~TR_CLK_DISABLE;

	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);



	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);