Commit 66fb1d5d authored by Edward Srouji's avatar Edward Srouji Committed by Leon Romanovsky
Browse files

IB/mlx5: Extend debug control for CC parameters 



This patch adds rtt_resp_dscp to the current debug controllability of
congestion control (CC) parameters.
rtt_resp_dscp can be read or written through debugfs.
If set, its value overwrites the DSCP of the generated RTT response.

Signed-off-by: default avatarEdward Srouji <edwards@nvidia.com>
Reviewed-by: default avatarMaor Gottlieb <maorg@nvidia.com>
Link: https://lore.kernel.org/r/1dcc3440ee53c688f19f579a051ded81a2aaa70a.1676538714.git.leon@kernel.org


Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent fd8958ef

drivers/infiniband/hw/mlx5/cong.c

+25 −3
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ 
enum mlx5_ib_cong_node_type {

	MLX5_IB_RROCE_ECN_RP = 1,

	MLX5_IB_RROCE_ECN_NP = 2,

	MLX5_IB_RROCE_GENERAL = 3,

};



static const char * const mlx5_ib_dbg_cc_name[] = {
@@ -61,6 +62,8 @@ static const char * const mlx5_ib_dbg_cc_name[] = { 
	"np_cnp_dscp",

	"np_cnp_prio_mode",

	"np_cnp_prio",

	"rtt_resp_dscp_valid",

	"rtt_resp_dscp",

};



#define MLX5_IB_RP_CLAMP_TGT_RATE_ATTR			BIT(1)
@@ -84,14 +87,18 @@ static const char * const mlx5_ib_dbg_cc_name[] = { 
#define MLX5_IB_NP_CNP_DSCP_ATTR			BIT(3)

#define MLX5_IB_NP_CNP_PRIO_MODE_ATTR			BIT(4)



#define MLX5_IB_GENERAL_RTT_RESP_DSCP_ATTR		BIT(0)



static enum mlx5_ib_cong_node_type

mlx5_ib_param_to_node(enum mlx5_ib_dbg_cc_types param_offset)

{

	if (param_offset >= MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE &&

	    param_offset <= MLX5_IB_DBG_CC_RP_GD)

	if (param_offset <= MLX5_IB_DBG_CC_RP_GD)

		return MLX5_IB_RROCE_ECN_RP;

	else



	if (param_offset <= MLX5_IB_DBG_CC_NP_CNP_PRIO)

		return MLX5_IB_RROCE_ECN_NP;



	return MLX5_IB_RROCE_GENERAL;

}



static u32 mlx5_get_cc_param_val(void *field, int offset)
@@ -157,6 +164,12 @@ static u32 mlx5_get_cc_param_val(void *field, int offset) 
	case MLX5_IB_DBG_CC_NP_CNP_PRIO:

		return MLX5_GET(cong_control_r_roce_ecn_np, field,

				cnp_802p_prio);

	case MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID:

		return MLX5_GET(cong_control_r_roce_general, field,

				rtt_resp_dscp_valid);

	case MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP:

		return MLX5_GET(cong_control_r_roce_general, field,

				rtt_resp_dscp);

	default:

		return 0;

	}
@@ -264,6 +277,15 @@ static void mlx5_ib_set_cc_param_mask_val(void *field, int offset, 
		MLX5_SET(cong_control_r_roce_ecn_np, field, cnp_prio_mode, 0);

		MLX5_SET(cong_control_r_roce_ecn_np, field, cnp_802p_prio, var);

		break;

	case MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID:

		*attr_mask |= MLX5_IB_GENERAL_RTT_RESP_DSCP_ATTR;

		MLX5_SET(cong_control_r_roce_general, field, rtt_resp_dscp_valid, var);

		break;

	case MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP:

		*attr_mask |= MLX5_IB_GENERAL_RTT_RESP_DSCP_ATTR;

		MLX5_SET(cong_control_r_roce_general, field, rtt_resp_dscp_valid, 1);

		MLX5_SET(cong_control_r_roce_general, field, rtt_resp_dscp, var);

		break;

	}

}

drivers/infiniband/hw/mlx5/mlx5_ib.h

+2 −0
Original line number Diff line number Diff line
@@ -888,6 +888,8 @@ enum mlx5_ib_dbg_cc_types { 
	MLX5_IB_DBG_CC_NP_CNP_DSCP,

	MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,

	MLX5_IB_DBG_CC_NP_CNP_PRIO,

	MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID,

	MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP,

	MLX5_IB_DBG_CC_MAX,

};

include/linux/mlx5/mlx5_ifc.h

+12 −0
Original line number Diff line number Diff line
@@ -2159,6 +2159,17 @@ struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 
	u8         reserved_at_360[0x4a0];

};



struct mlx5_ifc_cong_control_r_roce_general_bits {

	u8         reserved_at_0[0x80];



	u8         reserved_at_80[0x10];

	u8         rtt_resp_dscp_valid[0x1];

	u8         reserved_at_91[0x9];

	u8         rtt_resp_dscp[0x6];



	u8         reserved_at_a0[0x760];

};



struct mlx5_ifc_cong_control_802_1qau_rp_bits {

	u8         reserved_at_0[0x80];
@@ -4304,6 +4315,7 @@ union mlx5_ifc_cong_control_roce_ecn_auto_bits { 
	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;

	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;

	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;

	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;

	u8         reserved_at_0[0x800];

};