dt-bindings: arm: Convert CoreSight CPU debug to DT schema

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: CoreSight CPU Debug Component

maintainers:

  - Mathieu Poirier <mathieu.poirier@linaro.org>

  - Mike Leach <mike.leach@linaro.org>

  - Leo Yan <leo.yan@linaro.org>

  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |

  CoreSight CPU debug component are compliant with the ARMv8 architecture

  reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The

  external debug module is mainly used for two modes: self-hosted debug and

  external debug, and it can be accessed from mmio region from Coresight and

  eventually the debug module connects with CPU for debugging. And the debug

  module provides sample-based profiling extension, which can be used to sample

  CPU program counter, secure state and exception level, etc; usually every CPU

  has one dedicated debug module to be connected.

select:

  properties:

    compatible:

      contains:

        const: arm,coresight-cpu-debug

  required:

    - compatible

allOf:

  - $ref: /schemas/arm/primecell.yaml#

properties:

  compatible:

    items:

      - const: arm,coresight-cpu-debug

      - const: arm,primecell

  reg:

    maxItems: 1

  clocks:

    maxItems: 1

  clock-names:

    maxItems: 1

  cpu:

    description:

      A phandle to the cpu this debug component is bound to.

    $ref: /schemas/types.yaml#/definitions/phandle

  power-domains:

    maxItems: 1

    description:

      A phandle to the debug power domain if the debug logic has its own

      dedicated power domain. CPU idle states may also need to be separately

      constrained to keep CPU cores powered.

required:

  - compatible

  - reg

  - clocks

  - clock-names

  - cpu

unevaluatedProperties: false

examples:

  - |

    debug@f6590000 {

        compatible = "arm,coresight-cpu-debug", "arm,primecell";

        reg = <0xf6590000 0x1000>;

        clocks = <&sys_ctrl 1>;

        clock-names = "apb_pclk";

        cpu = <&cpu0>;

    };

...

* CoreSight CPU Debug Component:

CoreSight CPU debug component are compliant with the ARMv8 architecture

reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The

external debug module is mainly used for two modes: self-hosted debug and

external debug, and it can be accessed from mmio region from Coresight

and eventually the debug module connects with CPU for debugging. And the

debug module provides sample-based profiling extension, which can be used

to sample CPU program counter, secure state and exception level, etc;

usually every CPU has one dedicated debug module to be connected.

Required properties:

- compatible : should be "arm,coresight-cpu-debug"; supplemented with

               "arm,primecell" since this driver is using the AMBA bus

	       interface.

- reg : physical base address and length of the register set.

- clocks : the clock associated to this component.

- clock-names : the name of the clock referenced by the code. Since we are

                using the AMBA framework, the name of the clock providing

		the interconnect should be "apb_pclk" and the clock is

		mandatory. The interface between the debug logic and the

		processor core is clocked by the internal CPU clock, so it

		is enabled with CPU clock by default.

- cpu : the CPU phandle the debug module is affined to. Do not assume it

        to default to CPU0 if omitted.

Optional properties:

- power-domains: a phandle to the debug power domain. We use "power-domains"

                 binding to turn on the debug logic if it has own dedicated

		 power domain and if necessary to use "cpuidle.off=1" or

		 "nohlt" in the kernel command line or sysfs node to

		 constrain idle states to ensure registers in the CPU power

		 domain are accessible.

Example:

	debug@f6590000 {

		compatible = "arm,coresight-cpu-debug","arm,primecell";

		reg = <0 0xf6590000 0 0x1000>;

		clocks = <&sys_ctrl HI6220_DAPB_CLK>;

		clock-names = "apb_pclk";

		cpu = <&cpu0>;

	};

S:	Maintained

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git

F:	Documentation/ABI/testing/sysfs-bus-coresight-devices-*

F:	Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt

F:	Documentation/devicetree/bindings/arm/arm,coresight-*.yaml

F:	Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml

F:	Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml