Commit 66c3920d authored by Zhang Zekun's avatar Zhang Zekun
Browse files

Revert "iommu/arm-smmu-v3: Add a SYNC command to avoid broken page table prefetch" 

hulk inclusion
category: feature
bugzilla: https://gitee.com/src-openeuler/kernel/issues/I92MAE


CVE: NA

---------------------------------------------

This reverts commit 880e9284.

Signed-off-by: default avatarZhang Zekun <zhangzekun11@huawei.com>
parent a9c5e94c

arch/arm64/Kconfig

+0 −13
Original line number Diff line number Diff line
@@ -1185,19 +1185,6 @@ config HISILICON_ERRATUM_1980005 


	  If unsure, say N.



config HISILICON_ERRATUM_162100602

	bool "Hisilicon erratum 162100602"

	depends on ARM_SMMU_V3

	default y

	help

	  On Hisilicon LINXICORE9100 cores, SMMU pagetable prefetch features may

	  prefetch and use a invalid PTE even the PTE is valid at that time. This

	  will cause the device trigger fake pagefaults. If the SMMU works in

	  terminate mode, transactions which occur fake pagefaults will be aborted,

	  and could result in unexpected errors.



	  If unsure, say Y.



config QCOM_FALKOR_ERRATUM_1003

	bool "Falkor E1003: Incorrect translation due to ASID change"

	default y

arch/arm64/configs/openeuler_defconfig

+0 −1
Original line number Diff line number Diff line
@@ -428,7 +428,6 @@ CONFIG_FUJITSU_ERRATUM_010001=y 
CONFIG_HISILICON_ERRATUM_161600802=y

CONFIG_HISILICON_ERRATUM_162100125=y

# CONFIG_HISILICON_ERRATUM_1980005 is not set

CONFIG_HISILICON_ERRATUM_162100602=y

CONFIG_QCOM_FALKOR_ERRATUM_1003=y

CONFIG_QCOM_FALKOR_ERRATUM_1009=y

CONFIG_QCOM_QDF2400_ERRATUM_0065=y

arch/arm64/kernel/cpu_errata.c

+0 −14
Original line number Diff line number Diff line
@@ -360,13 +360,6 @@ static const struct midr_range hisilicon_erratum_162100125_cpus[] = { 
};

#endif



#ifdef CONFIG_HISILICON_ERRATUM_162100602

static const struct midr_range hisilicon_erratum_162100602_cpus[] = {

	MIDR_REV(MIDR_HISI_LINXICORE9100, 0, 0),

	{},

};

#endif



#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003

static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {

	{
@@ -598,13 +591,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100125_cpus),

	},

#endif

#ifdef CONFIG_HISILICON_ERRATUM_162100602

	{

		.desc = "Hisilicon erratum 162100602",

		.capability = ARM64_WORKAROUND_HISILICON_ERRATUM_162100602,

		ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100602_cpus),

	},

#endif

#ifdef CONFIG_HISILICON_ERRATUM_1980005

	{

		.desc = "Hisilicon erratum 1980005 (IDC)",

arch/arm64/tools/cpucaps

+0 −1
Original line number Diff line number Diff line
@@ -105,7 +105,6 @@ WORKAROUND_SPECULATIVE_AT 
WORKAROUND_HISILICON_ERRATUM_162100125

WORKAROUND_HISI_HIP08_RU_PREFETCH

WORKAROUND_HISILICON_1980005

WORKAROUND_HISILICON_ERRATUM_162100602

KABI_RESERVE_1

KABI_RESERVE_2

KABI_RESERVE_3

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+0 −20
Original line number Diff line number Diff line
@@ -2776,23 +2776,6 @@ static void arm_smmu_iotlb_sync(struct iommu_domain *domain, 
				      gather->pgsize, true, smmu_domain);

}



#ifdef CONFIG_HISILICON_ERRATUM_162100602

static void arm_smmu_iotlb_sync_map(struct iommu_domain *domain,

				unsigned long iova, size_t size)

{

	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);

	size_t granule_size;



	if (!cpus_have_const_cap(ARM64_WORKAROUND_HISILICON_ERRATUM_162100602))

		return;



	granule_size = 1 <<  __ffs(smmu_domain->domain.pgsize_bitmap);



	/* Add a SYNC command to sync io-pgtale to avoid errors in pgtable prefetch*/

	arm_smmu_tlb_inv_range_domain(iova, granule_size, granule_size, true, smmu_domain);

}

#endif



static phys_addr_t

arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)

{
@@ -3356,9 +3339,6 @@ static struct iommu_ops arm_smmu_ops = { 
		.unmap_pages		= arm_smmu_unmap_pages,

		.flush_iotlb_all	= arm_smmu_flush_iotlb_all,

		.iotlb_sync		= arm_smmu_iotlb_sync,

#ifdef CONFIG_HISILICON_ERRATUM_162100602

		.iotlb_sync_map		= arm_smmu_iotlb_sync_map,

#endif

		.iova_to_phys		= arm_smmu_iova_to_phys,

		.enable_nesting		= arm_smmu_enable_nesting,

#ifdef CONFIG_ARM_SMMU_V3_HTTU