Unverified Commit 66942646 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!3415 Some bugfix for hns3 

Merge Pull Request from: @svishen 
 
This pr fixes some hns3 bugfix

（1）The serdes serial loopback test will be disable in certain scenarios.
（2）Fixes the capability is miss for hisilicon device 200G link interface。
（3）Add judgement for 1D tours feature which not supported for board v4 version.

issue:
https://gitee.com/openeuler/kernel/issues/I8OH8B?from=project-issue 
 
Link:https://gitee.com/openeuler/kernel/pulls/3415

 

Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 48276059 e526b8bd

drivers/net/ethernet/hisilicon/hns3/hnae3.h

+2 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ 
#define HNAE3_DEVICE_VERSION_V1   0x00020

#define HNAE3_DEVICE_VERSION_V2   0x00021

#define HNAE3_DEVICE_VERSION_V3   0x00030

#define HNAE3_DEVICE_VERSION_V4   0x00032



#define HNAE3_PCI_REVISION_BIT_SIZE		8
@@ -453,6 +454,7 @@ struct hnae3_dev_specs { 
	u8 tnl_num;

	u16 guid_tbl_space;

	u16 ip_tbl_space;

	u8 hilink_version;

};



struct hnae3_client_ops {

drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

+2 −0
Original line number Diff line number Diff line
@@ -1099,6 +1099,8 @@ hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos) 
	*pos += scnprintf(buf + *pos, len - *pos,

			  "TX timeout threshold: %d seconds\n",

			  dev->watchdog_timeo / HZ);

	*pos += scnprintf(buf + *pos, len - *pos, "Hilink Version: %u\n",

			  dev_specs->hilink_version);

}



static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+2 −1
Original line number Diff line number Diff line
@@ -868,7 +868,8 @@ struct hclge_dev_specs_1_cmd { 
	__le16 guid_tbl_space;

	__le16 ip_tbl_space;

	u8 tnl_num;

	u8 rsv2[5];

	u8 hilink_version;

	u8 rsv2[4];

};



/* mac speed type defined in firmware command */

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c

+6 −0
Original line number Diff line number Diff line
@@ -281,6 +281,9 @@ static int hclge_set_torus_param(struct hclge_dev *hdev, void *data, 
	struct hnae3_torus_param *param = (struct hnae3_torus_param *)data;

	int ret;



	if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V4)

		return -EOPNOTSUPP;



	if (length != sizeof(struct hnae3_torus_param))

		return -EINVAL;
@@ -318,6 +321,9 @@ static int hclge_get_torus_param(struct hclge_dev *hdev, void *data, 
	struct hclge_desc desc;

	int ret;



	if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V4)

		return -EOPNOTSUPP;



	if (length != sizeof(struct hnae3_torus_param))

		return -EINVAL;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+25 −12
Original line number Diff line number Diff line
@@ -704,8 +704,12 @@ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 
			handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;

		}



		if (hdev->ae_dev->dev_specs.hilink_version !=

		    HCLGE_HILINK_H60) {

			count += 1;

			handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;

		}



		count += 1;

		handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;

		count += 1;
@@ -958,7 +962,7 @@ static const struct hclge_speed_bit_map speed_bit_map[] = { 
	{HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT},

	{HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS},

	{HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS},

	{HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT},

	{HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS},

};



static int hclge_get_speed_bit(u32 speed, u32 *speed_bit)
@@ -1014,7 +1018,7 @@ static void hclge_update_fec_support(struct hclge_mac *mac) 
				 mac->supported);

}



static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[8] = {

static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = {

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT},

	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT},

	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT},
@@ -1022,10 +1026,12 @@ static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[8] = { 
	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT},

	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_EXT_BIT,

	 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT},

};



static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[6] = {

static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = {

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT},

	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT},

	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT},
@@ -1033,11 +1039,13 @@ static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[6] = { 
	 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT,

	 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT,

	{HCLGE_SUPPORT_200G_R4_EXT_BIT,

	 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_BIT,

	 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT},

};



static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[8] = {

static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = {

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT},

	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT},

	{HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT},
@@ -1045,10 +1053,12 @@ static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[8] = { 
	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT},

	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_EXT_BIT,

	 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT},

};



static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[9] = {

static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = {

	{HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT},

	{HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT},

	{HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT},
@@ -1057,7 +1067,9 @@ static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[9] = { 
	{HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT},

	{HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT},

	{HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT},

	{HCLGE_SUPPORT_200G_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_EXT_BIT,

	 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},

	{HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT},

};



static void hclge_convert_setting_sr(u16 speed_ability,
@@ -1228,7 +1240,7 @@ static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 


static u32 hclge_get_max_speed(u16 speed_ability)

{

	if (speed_ability & HCLGE_SUPPORT_200G_BIT)

	if (speed_ability & HCLGE_SUPPORT_200G_BITS)

		return HCLGE_MAC_SPEED_200G;



	if (speed_ability & HCLGE_SUPPORT_100G_BITS)
@@ -1424,6 +1436,7 @@ static void hclge_parse_dev_specs(struct hclge_dev *hdev, 
	ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size);

	ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size);

	ae_dev->dev_specs.tnl_num = req1->tnl_num;

	ae_dev->dev_specs.hilink_version = req1->hilink_version;

#ifdef CONFIG_HNS3_UBL

	if (hnae3_dev_ubl_supported(ae_dev)) {

		ae_dev->dev_specs.guid_tbl_space =