Commit 6688a4dd authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvc0/gr: fixup the mmio list register writes for 0xc1 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 4c5df493

drivers/gpu/drm/nouveau/nvc0_graph.c

+32 −9
Original line number Diff line number Diff line
@@ -157,8 +157,8 @@ nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan) 
	struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);

	struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];

	struct drm_device *dev = chan->dev;

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	int i = 0, gpc, tp, ret;

	u32 magic;



	ret = nouveau_gpuobj_new(dev, chan, 0x2000, 256, NVOBJ_FLAG_VM,

				 &grch->unk408004);
@@ -207,14 +207,37 @@ nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan) 
	nv_wo32(grch->mmio, i++ * 4, 0x0041880c);

	nv_wo32(grch->mmio, i++ * 4, 0x80000018);



	magic = 0x02180000;

	if (dev_priv->chipset != 0xc1) {

		u32 magic = 0x02180000;

		nv_wo32(grch->mmio, i++ * 4, 0x00405830);

		nv_wo32(grch->mmio, i++ * 4, magic);

		for (gpc = 0; gpc < priv->gpc_nr; gpc++) {

		for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x0324) {

			u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);

			for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {

				u32 reg = TP_UNIT(gpc, tp, 0x520);

				nv_wo32(grch->mmio, i++ * 4, reg);

				nv_wo32(grch->mmio, i++ * 4, magic);

				magic += 0x0324;

			}

		}

	} else {

		u32 magic = 0x02180000;

		nv_wo32(grch->mmio, i++ * 4, 0x00405830);

		nv_wo32(grch->mmio, i++ * 4, magic | 0x0000218);

		nv_wo32(grch->mmio, i++ * 4, 0x004064c4);

		nv_wo32(grch->mmio, i++ * 4, 0x0086ffff);

		for (gpc = 0; gpc < priv->gpc_nr; gpc++) {

			for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {

				u32 reg = TP_UNIT(gpc, tp, 0x520);

				nv_wo32(grch->mmio, i++ * 4, reg);

				nv_wo32(grch->mmio, i++ * 4, (1 << 28) | magic);

				magic += 0x0324;

			}

			for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {

				u32 reg = TP_UNIT(gpc, tp, 0x544);

				nv_wo32(grch->mmio, i++ * 4, reg);

				nv_wo32(grch->mmio, i++ * 4, magic);

				magic += 0x0324;

			}

		}

	}