Commit 668756f7 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g044: Add P2 Clock support 



Add support for P2 clock which is sourced from pll3_div2_4_2.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-5-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent fd8c3f6c

drivers/clk/renesas/r9a07g044-cpg.c

+4 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ enum clk_ids { 
	CLK_PLL3,

	CLK_PLL3_DIV2,

	CLK_PLL3_DIV2_4,

	CLK_PLL3_DIV2_4_2,

	CLK_PLL3_DIV4,

	CLK_PLL4,

	CLK_PLL5,
@@ -68,6 +69,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 


	DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),

	DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),

	DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),

	DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),



	/* Core output clk */
@@ -77,6 +79,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { 
	DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),

	DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,

		DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),

	DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,

		DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),

};



static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {

drivers/clk/renesas/renesas-rzg2l-cpg.h

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#define DDIV_PACK(offset, bitpos, size) \

		(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))

#define DIVPL2A		DDIV_PACK(CPG_PL2_DDIV, 0, 3)

#define DIVPL3A		DDIV_PACK(CPG_PL3A_DDIV, 0, 3)

#define DIVPL3B		DDIV_PACK(CPG_PL3A_DDIV, 4, 3)



/**