Commit 66637ab1 authored by Guangbin Huang's avatar Guangbin Huang Committed by Will Deacon
Browse files

drivers/perf: hisi: add driver for HNS3 PMU



HNS3(HiSilicon Network System 3) PMU is RCiEP device in HiSilicon SoC NIC,
supports collection of performance statistics such as bandwidth, latency,
packet rate and interrupt rate.

NIC of each SICL has one PMU device for it. Driver registers each PMU
device to perf, and exports information of supported events, filter mode of
each event, bdf range, hardware clock frequency, identifier and so on via
sysfs.

Each PMU device has its own registers of control, counters and interrupt,
and it supports 8 hardware events, each hardward event has its own
registers for configuration, counters and interrupt.

Filter options contains:
config       - select event
port         - select physical port of nic
tc           - select tc(must be used with port)
func         - select PF/VF
queue        - select queue of PF/VF(must be used with func)
intr         - select interrupt number(must be used with func)
global       - select all functions of IO DIE

Signed-off-by: default avatarGuangbin Huang <huangguangbin2@huawei.com>
Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Reviewed-by: default avatarShaokun Zhang <zhangshaokun@hisilicon.com>
Link: https://lore.kernel.org/r/20220628063419.38514-3-huangguangbin2@huawei.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 39915b6b
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+6 −0
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@@ -8944,6 +8944,12 @@ F: Documentation/admin-guide/perf/hisi-pcie-pmu.rst
F:	Documentation/admin-guide/perf/hisi-pmu.rst
F:	drivers/perf/hisilicon
HISILICON HNS3 PMU DRIVER
M:	Guangbin Huang <huangguangbin2@huawei.com>
S:	Supported
F:	Documentation/admin-guide/perf/hns3-pmu.rst
F:	drivers/perf/hisilicon/hns3_pmu.c
HISILICON QM AND ZIP Controller DRIVER
M:	Zhou Wang <wangzhou1@hisilicon.com>
L:	linux-crypto@vger.kernel.org
+10 −0
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@@ -14,3 +14,13 @@ config HISI_PCIE_PMU
	  RCiEP devices.
	  Adds the PCIe PMU into perf events system for monitoring latency,
	  bandwidth etc.

config HNS3_PMU
	tristate "HNS3 PERF PMU"
	depends on ARM64 || COMPILE_TEST
	depends on PCI
	help
	  Provide support for HNS3 performance monitoring unit (PMU) RCiEP
	  devices.
	  Adds the HNS3 PMU into perf events system for monitoring latency,
	  bandwidth etc.
+1 −0
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@@ -4,3 +4,4 @@ obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o \
			  hisi_uncore_pa_pmu.o hisi_uncore_cpa_pmu.o

obj-$(CONFIG_HISI_PCIE_PMU) += hisi_pcie_pmu.o
obj-$(CONFIG_HNS3_PMU) += hns3_pmu.o
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@@ -230,6 +230,7 @@ enum cpuhp_state {
	CPUHP_AP_PERF_ARM_HISI_PA_ONLINE,
	CPUHP_AP_PERF_ARM_HISI_SLLC_ONLINE,
	CPUHP_AP_PERF_ARM_HISI_PCIE_PMU_ONLINE,
	CPUHP_AP_PERF_ARM_HNS3_PMU_ONLINE,
	CPUHP_AP_PERF_ARM_L2X0_ONLINE,
	CPUHP_AP_PERF_ARM_QCOM_L2_ONLINE,
	CPUHP_AP_PERF_ARM_QCOM_L3_ONLINE,