Commit 665a7b04 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Feed the DPLL output freq back into crtc_state 



Fill port_clock and hw.adjusted_mode.crtc_clock with the actual
frequency we're going to be getting from the hardware. This will
let us accurately compute all derived state that depends on those.

v2: Reintroduce iCLKIP WARN
v3: Try to deal with VLV/BXT DSI PLL as well

Reviewed-by: Jani Nikula <jani.nikula@intel.com> #v1
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220907091057.11572-8-ville.syrjala@linux.intel.com
parent e95132ef

drivers/gpu/drm/i915/display/intel_crt.c

+3 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ 
#include "intel_gmbus.h"

#include "intel_hotplug.h"

#include "intel_pch_display.h"

#include "intel_pch_refclk.h"



/* Here's the desired hotplug mode */

#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
@@ -444,6 +445,8 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder, 
	/* FDI must always be 2.7 GHz */

	pipe_config->port_clock = 135000 * 2;



	adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);



	return 0;

}

drivers/gpu/drm/i915/display/intel_dpll.c

+57 −3
Original line number Diff line number Diff line
@@ -938,12 +938,25 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state, 
		intel_atomic_get_new_crtc_state(state, crtc);

	struct intel_encoder *encoder =

		intel_get_crtc_new_encoder(state, crtc_state);

	int ret;



	if (DISPLAY_VER(dev_priv) < 11 &&

	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

		return 0;



	return intel_compute_shared_dplls(state, crtc, encoder);

	ret = intel_compute_shared_dplls(state, crtc, encoder);

	if (ret)

		return ret;



	/* FIXME this is a mess */

	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

		return 0;



	/* CRT dotclock is determined via other means */

	if (!crtc_state->has_pch_encoder)

		crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);



	return 0;

}



static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -969,8 +982,15 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state, 
		intel_atomic_get_new_crtc_state(state, crtc);

	struct intel_encoder *encoder =

		intel_get_crtc_new_encoder(state, crtc_state);

	int ret;



	ret = intel_mpllb_calc_state(crtc_state, encoder);

	if (ret)

		return ret;



	return intel_mpllb_calc_state(crtc_state, encoder);

	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);



	return 0;

}



static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
@@ -1096,6 +1116,7 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, 
		intel_atomic_get_new_crtc_state(state, crtc);

	const struct intel_limit *limit;

	int refclk = 120000;

	int ret;



	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */

	if (!crtc_state->has_pch_encoder)
@@ -1132,7 +1153,14 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state, 
	ilk_compute_dpll(crtc_state, &crtc_state->dpll,

			 &crtc_state->dpll);



	return intel_compute_shared_dplls(state, crtc, NULL);

	ret = intel_compute_shared_dplls(state, crtc, NULL);

	if (ret)

		return ret;



	crtc_state->port_clock = crtc_state->dpll.dot;

	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);



	return ret;

}



static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
@@ -1198,6 +1226,13 @@ static int chv_crtc_compute_clock(struct intel_atomic_state *state, 


	chv_compute_dpll(crtc_state);



	/* FIXME this is a mess */

	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

		return 0;



	crtc_state->port_clock = crtc_state->dpll.dot;

	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);



	return 0;

}
@@ -1217,6 +1252,13 @@ static int vlv_crtc_compute_clock(struct intel_atomic_state *state, 


	vlv_compute_dpll(crtc_state);



	/* FIXME this is a mess */

	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))

		return 0;



	crtc_state->port_clock = crtc_state->dpll.dot;

	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);



	return 0;

}
@@ -1259,6 +1301,9 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state, 
	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

			  &crtc_state->dpll);



	crtc_state->port_clock = crtc_state->dpll.dot;

	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);



	return 0;

}
@@ -1292,6 +1337,9 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state, 
	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

			  &crtc_state->dpll);



	crtc_state->port_clock = crtc_state->dpll.dot;

	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);



	return 0;

}
@@ -1325,6 +1373,9 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state, 
	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

			  &crtc_state->dpll);



	crtc_state->port_clock = crtc_state->dpll.dot;

	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);



	return 0;

}
@@ -1360,6 +1411,9 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, 
	i8xx_compute_dpll(crtc_state, &crtc_state->dpll,

			  &crtc_state->dpll);



	crtc_state->port_clock = crtc_state->dpll.dot;

	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);



	return 0;

}

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+23 −1
Original line number Diff line number Diff line
@@ -949,6 +949,7 @@ static int 
hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,

			   struct intel_crtc *crtc)

{

	struct drm_i915_private *i915 = to_i915(state->base.dev);

	struct intel_crtc_state *crtc_state =

		intel_atomic_get_new_crtc_state(state, crtc);

	unsigned int p, n2, r2;
@@ -960,6 +961,9 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state, 
		WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |

		WRPLL_DIVIDER_POST(p);



	crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL,

							&crtc_state->dpll_hw_state);



	return 0;

}
@@ -1723,6 +1727,9 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) 
	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;

	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;



	crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,

							&crtc_state->dpll_hw_state);



	return 0;

}
@@ -2275,11 +2282,20 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) 
static int

bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);

	struct dpll clk_div = {};

	int ret;



	bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);



	return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);

	ret = bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);

	if (ret)

		return ret;



	crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL,

						      &crtc_state->dpll_hw_state);



	return 0;

}



static int bxt_compute_dpll(struct intel_atomic_state *state,
@@ -3197,6 +3213,9 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state, 


	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);



	crtc_state->port_clock = icl_ddi_combo_pll_get_freq(dev_priv, NULL,

							    &port_dpll->hw_state);



	return 0;

}
@@ -3282,6 +3301,9 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, 
	if (ret)

		return ret;



	crtc_state->port_clock = icl_ddi_mg_pll_get_freq(dev_priv, NULL,

							 &port_dpll->hw_state);



	return 0;

}

drivers/gpu/drm/i915/display/intel_pch_refclk.c

+10 −0
Original line number Diff line number Diff line
@@ -167,6 +167,15 @@ static void lpt_compute_iclkip(struct iclkip_params *p, int clock) 
	}

}



int lpt_iclkip(const struct intel_crtc_state *crtc_state)

{

	struct iclkip_params p;



	lpt_compute_iclkip(&p, crtc_state->hw.adjusted_mode.crtc_clock);



	return lpt_iclkip_freq(&p);

}



/* Program iCLKIP clock to the desired frequency */

void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)

{
@@ -179,6 +188,7 @@ void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) 
	lpt_disable_iclkip(dev_priv);



	lpt_compute_iclkip(&p, clock);

	drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock);



	/* This should not happen with any sane values */

	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &

drivers/gpu/drm/i915/display/intel_pch_refclk.h

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ struct intel_crtc_state; 
void lpt_program_iclkip(const struct intel_crtc_state *crtc_state);

void lpt_disable_iclkip(struct drm_i915_private *dev_priv);

int lpt_get_iclkip(struct drm_i915_private *dev_priv);

int lpt_iclkip(const struct intel_crtc_state *crtc_state);



void intel_init_pch_refclk(struct drm_i915_private *dev_priv);

void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);