Commit 6650ebcb authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_* 



Prefer acronym-based naming to be in line with the rest of the driver.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220112111740.1208374-1-jani.nikula@intel.com
parent 2616be2e

drivers/gpu/drm/i915/display/intel_bw.c

+5 −8
Original line number Diff line number Diff line
@@ -75,8 +75,7 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, 
	u16 dclk;

	int ret;



	ret = sandybridge_pcode_read(dev_priv,

				     ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

	ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

			     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),

			     &val, &val2);

	if (ret)
@@ -102,10 +101,8 @@ static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv, 
	int ret;

	int i;



	ret = sandybridge_pcode_read(dev_priv,

				     ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

				     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO,

				     &val, NULL);

	ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |

			     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);

	if (ret)

		return ret;

drivers/gpu/drm/i915/display/intel_cdclk.c

+14 −16
Original line number Diff line number Diff line
@@ -805,8 +805,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 
		     "trying to change cdclk frequency with cdclk not enabled\n"))

		return;



	ret = sandybridge_pcode_write(dev_priv,

				      BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);

	ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);

	if (ret) {

		drm_err(&dev_priv->drm,

			"failed to inform pcode about cdclk change\n");
@@ -834,7 +833,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 
			 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))

		drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");



	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,

	snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,

			cdclk_config->voltage_level);



	intel_de_write(dev_priv, CDCLK_FREQ,
@@ -1138,7 +1137,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, 
	intel_de_posting_read(dev_priv, CDCLK_CTL);



	/* inform PCU of the change */

	sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,

	snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,

			cdclk_config->voltage_level);



	intel_update_cdclk(dev_priv);
@@ -1717,10 +1716,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
		 * BSpec requires us to wait up to 150usec, but that leads to

		 * timeouts; the 2ms used here is based on experiment.

		 */

		ret = sandybridge_pcode_write_timeout(dev_priv,

		ret = snb_pcode_write_timeout(dev_priv,

					      HSW_PCODE_DE_WRITE_FREQ_REQ,

					      0x80000000, 150, 2);



	if (ret) {

		drm_err(&dev_priv->drm,

			"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
@@ -1781,7 +1779,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
		intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));



	if (DISPLAY_VER(dev_priv) >= 11) {

		ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,

		ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,

				      cdclk_config->voltage_level);

	} else {

		/*
@@ -1790,7 +1788,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
		 * FIXME: Waiting for the request completion could be delayed

		 * until the next PCODE request based on BSpec.

		 */

		ret = sandybridge_pcode_write_timeout(dev_priv,

		ret = snb_pcode_write_timeout(dev_priv,

					      HSW_PCODE_DE_WRITE_FREQ_REQ,

					      cdclk_config->voltage_level,

					      150, 2);

drivers/gpu/drm/i915/display/intel_display.c

+3 −3
Original line number Diff line number Diff line
@@ -1118,7 +1118,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) 
	drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));



	if (IS_BROADWELL(dev_priv)) {

		drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,

		drm_WARN_ON(dev, snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,

						 IPS_ENABLE | IPS_PCODE_CONTROL));

		/* Quoting Art Runyan: "its not safe to expect any particular

		 * value in IPS_CTL bit 31 after enabling IPS through the
@@ -1149,7 +1149,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state) 


	if (IS_BROADWELL(dev_priv)) {

		drm_WARN_ON(dev,

			    sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));

			    snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));

		/*

		 * Wait for PCODE to finish disabling IPS. The BSpec specified

		 * 42ms timeout value leads to occasional timeouts so use 100ms

drivers/gpu/drm/i915/display/intel_display_power.c

+4 −7
Original line number Diff line number Diff line
@@ -683,9 +683,8 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915) 
	int ret, tries = 0;



	while (1) {

		ret = sandybridge_pcode_write_timeout(i915,

						      ICL_PCODE_EXIT_TCCOLD,

						      0, 250, 1);

		ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,

					      250, 1);

		if (ret != -EAGAIN || ++tries == 3)

			break;

		msleep(1);
@@ -4053,8 +4052,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block) 
		 * Spec states that we should timeout the request after 200us

		 * but the function below will timeout after 500us

		 */

		ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,

					     &high_val);

		ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);

		if (ret == 0) {

			if (block &&

			    (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
@@ -5469,8 +5467,7 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv) 
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)

{

	if (IS_HASWELL(dev_priv)) {

		if (sandybridge_pcode_write(dev_priv,

					    GEN6_PCODE_WRITE_D_COMP, val))

		if (snb_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))

			drm_dbg_kms(&dev_priv->drm,

				    "Failed to write to D_COMP\n");

	} else {

drivers/gpu/drm/i915/display/intel_hdcp.c

+1 −2
Original line number Diff line number Diff line
@@ -297,8 +297,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) 
	 * Mailbox interface.

	 */

	if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {

		ret = sandybridge_pcode_write(dev_priv,

					      SKL_PCODE_LOAD_HDCP_KEYS, 1);

		ret = snb_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);

		if (ret) {

			drm_err(&dev_priv->drm,

				"Failed to initiate HDCP key load (%d)\n",