Commit 6619ec0b authored by Kai Ye's avatar Kai Ye Committed by Zheng Zengkai
Browse files

crypto: hisilicon/sec - modify the hardware endian configuration 

mainline inclusion
from mainline-master
commit a5262610
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I475XT?from=project-issue
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git/commit/?id=a52626106d6f7edf3d106c065e13a0313cfeb82f



----------------------------------------------------------------------

When the endian configuration of the hardware is abnormal, it will
cause the SEC engine is faulty that reports empty message. And it
will affect the normal function of the hardware. Currently the soft
configuration method can't restore the faulty device. The endian
needs to be configured according to the system properties. So fix it.

Signed-off-by: default avatarKai Ye <yekai13@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
Reviewed-by: default avatarHao Fang <fanghao11@huawei.com>
Reviewed-by: default avatarMingqiang Ling <lingmingqiang@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent 65f65013

drivers/crypto/hisilicon/sec2/sec.h

+0 −5
Original line number Diff line number Diff line
@@ -157,11 +157,6 @@ struct sec_ctx { 
	struct device *dev;

};



enum sec_endian {

	SEC_LE = 0,

	SEC_32BE,

	SEC_64BE

};



enum sec_debug_file_index {

	SEC_CLEAR_ENABLE,

drivers/crypto/hisilicon/sec2/sec_main.c

+9 −22
Original line number Diff line number Diff line
@@ -318,31 +318,20 @@ static const struct pci_device_id sec_dev_ids[] = { 
};

MODULE_DEVICE_TABLE(pci, sec_dev_ids);



static u8 sec_get_endian(struct hisi_qm *qm)

static void sec_set_endian(struct hisi_qm *qm)

{

	u32 reg;



	/*

	 * As for VF, it is a wrong way to get endian setting by

	 * reading a register of the engine

	 */

	if (qm->pdev->is_virtfn) {

		dev_err_ratelimited(&qm->pdev->dev,

				    "cannot access a register in VF!\n");

		return SEC_LE;

	}

	reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);

	/* BD little endian mode */

	if (!(reg & BIT(0)))

		return SEC_LE;

	reg &= ~(BIT(1) | BIT(0));

	if (!IS_ENABLED(CONFIG_64BIT))

		reg |= BIT(1);



	/* BD 32-bits big endian mode */

	else if (!(reg & BIT(1)))

		return SEC_32BE;



	/* BD 64-bits big endian mode */

	else

		return SEC_64BE;

	if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))

		reg |= BIT(0);



	writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);

}



static void sec_open_sva_prefetch(struct hisi_qm *qm)
@@ -463,9 +452,7 @@ static int sec_engine_init(struct hisi_qm *qm) 
		       qm->io_base + SEC_BD_ERR_CHK_EN_REG3);



	/* config endian */

	reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);

	reg |= sec_get_endian(qm);

	writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);

	sec_set_endian(qm);



	sec_enable_clock_gate(qm);