Commit 65ec0a7d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "There is a lot going on!

  Core changes:

   - A semantic change to handle pinmux and pinconf in explicit order
     while up until now we depended on the semantic order in the device
     tree. The device tree is a functional programming language and does
     not imply any order, so the right thing is for the pin control core
     to provide these semantics.

   - Add a new pinmux-select debugfs file which makes it possible to go
     in and select functions for a pin manually (iteratively, at the
     prompt) for debugging purposes.

   - Fixes to gpio regmap handling for a new pin control driver making
     use of regmap-gpio.

   - Use octal permissions on debugfs files.

  New drivers:

   - A massive rewrite of the former custom pin control driver for MIPS
     Broadcom devices to instead use the pin control subsystem. New pin
     control drivers for BCM6345, BCM6328, BCM6358, BCM6362, BCM6368,
     BCM63268 and BCM6318 SoC variants are implemented.

   - Support for PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B
     in the Qualcomm PMIC GPIO driver. Also the two GPIOs on PM8008 are
     supported.

   - Support for the Rockchip RK3568/RK3566 pin controller.

   - Support for Ingenic JZ4730, JZ4750, JZ4755, JZ4775 and X2000.

   - Support for Mediatek MTK8195.

   - Add a new Xilinx ZynqMP pin control driver.

  Driver improvements and non-urgent fixes:

   - Modularization and improvements of the Rockchip drivers.

   - Some new pins added to the description of new Renesas SoCs.

   - Clarifications of the GPIO base calculation in the Intel driver.

   - Fix the function names for the MPP54 and MPP55 pins in the Armada
     CP110 pin controller.

   - GPIO wakeup interrupt map for Qualcomm SC7280 and SM8350.

   - Support for ACPI probing of the Qualcomm SC8180x.

   - Fix interrupt clear status on rockchip

   - Fix some missing pins on the Ingenic JZ4770, some semantic fixes
     for the behaviour of the Ingenic pin controller. Add DMIC pins for
     JZ4780, X1000, X1500 and X1830.

   - A slew of janitorial like of_node_put() calls"

* tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
  pinctrl: Add Xilinx ZynqMP pinctrl driver support
  firmware: xilinx: Add pinctrl support
  pinctrl: rockchip: do coding style for mux route struct
  pinctrl: Add PIN_CONFIG_MODE_PWM to enum pin_config_param
  pinctrl: Introduce MODE group in enum pin_config_param
  pinctrl: Keep enum pin_config_param ordered by name
  dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver
  pinctrl: core: Fix kernel doc string for pin_get_name()
  pinctrl: mediatek: use spin lock in mtk_rmw
  pinctrl: add drive for I2C related pins on MT8195
  pinctrl: add pinctrl driver on mt8195
  dt-bindings: pinctrl: mt8195: add pinctrl file and binding document
  pinctrl: Ingenic: Add pinctrl driver for X2000.
  pinctrl: Ingenic: Add pinctrl driver for JZ4775.
  pinctrl: Ingenic: Add pinctrl driver for JZ4755.
  pinctrl: Ingenic: Add pinctrl driver for JZ4750.
  pinctrl: Ingenic: Add pinctrl driver for JZ4730.
  dt-bindings: pinctrl: Add bindings for new Ingenic SoCs.
  pinctrl: Ingenic: Reformat the code.
  pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs.
  ...
parents 592fa953 8b242ca7

Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt

+2 −2
Original line number Diff line number Diff line
@@ -142,8 +142,8 @@ mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg( 
mpp51	51	gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10)

mpp52	52	gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq)

mpp53	53	gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led)

mpp54	54	gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio(wr_protect)

mpp55	55	gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio(card_detect)

mpp54	54	gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio_wp(wr_protect)

mpp55	55	gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio_cd(card_detect)

mpp56	56	gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk)

mpp57	57	gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd)

mpp58	58	gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0)

Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.txt

deleted100644 → 0
+0 −46
Original line number Diff line number Diff line 
Bindings for the Broadcom's brcm,bcm6345-gpio memory-mapped GPIO controllers.



These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345

are the only ones which don't need a pinctrl driver.

BCM6338 have 8-bit data and dirout registers, where GPIO state can be read

and/or written, and the direction changed from input to output.

BCM6345 have 16-bit data and dirout registers, where GPIO state can be read

and/or written, and the direction changed from input to output.



Required properties:

	- compatible: should be "brcm,bcm6345-gpio"

	- reg-names: must contain

		"dat" - data register

		"dirout" - direction (output) register

	- reg: address + size pairs describing the GPIO register sets;

		order must correspond with the order of entries in reg-names

	- #gpio-cells: must be set to 2. The first cell is the pin number and

			the second cell is used to specify the gpio polarity:

			0 = active high

			1 = active low

	- gpio-controller: Marks the device node as a gpio controller.



Optional properties:

	- native-endian: use native endian memory.



Examples:

	- BCM6338:

	gpio: gpio-controller@fffe0407 {

		compatible = "brcm,bcm6345-gpio";

		reg-names = "dirout", "dat";

		reg = <0xfffe0407 1>, <0xfffe040f 1>;



		#gpio-cells = <2>;

		gpio-controller;

	};



	- BCM6345:

	gpio: gpio-controller@fffe0406 {

		compatible = "brcm,bcm6345-gpio";

		reg-names = "dirout", "dat";

		reg = <0xfffe0406 2>, <0xfffe040a 2>;

		native-endian;



		#gpio-cells = <2>;

		gpio-controller;

	};

Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml

0 → 100644
+86 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Broadcom BCM6345 GPIO controller



maintainers:

  - Álvaro Fernández Rojas <noltari@gmail.com>

  - Jonas Gorski <jonas.gorski@gmail.com>



description: |+

  Bindings for Broadcom's BCM63xx memory-mapped GPIO controllers.



  These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345

  are the only ones which don't need a pinctrl driver.



  BCM6338 have 8-bit data and dirout registers, where GPIO state can be read

  and/or written, and the direction changed from input to output.

  BCM6345 have 16-bit data and dirout registers, where GPIO state can be read

  and/or written, and the direction changed from input to output.

  BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data

  and dirout registers, where GPIO state can be read and/or written, and the

  direction changed from input to output.



properties:

  compatible:

    enum:

      - brcm,bcm6318-gpio

      - brcm,bcm6328-gpio

      - brcm,bcm6345-gpio

      - brcm,bcm6358-gpio

      - brcm,bcm6362-gpio

      - brcm,bcm6368-gpio

      - brcm,bcm63268-gpio



  gpio-controller: true



  "#gpio-cells":

    const: 2



  gpio-ranges:

    maxItems: 1



  native-endian: true



  reg:

    maxItems: 2



  reg-names:

    items:

      - const: dirout

      - const: dat



required:

  - compatible

  - reg

  - reg-names

  - gpio-controller

  - '#gpio-cells'



additionalProperties: false



examples:

  - |

    gpio@fffe0406 {

      compatible = "brcm,bcm6345-gpio";

      reg-names = "dirout", "dat";

      reg = <0xfffe0406 2>, <0xfffe040a 2>;

      native-endian;



      gpio-controller;

      #gpio-cells = <2>;

    };



  - |

    gpio@0 {

      compatible = "brcm,bcm63268-gpio";

      reg-names = "dirout", "dat";

      reg = <0x0 0x8>, <0x8 0x8>;



      gpio-controller;

      gpio-ranges = <&pinctrl 0 0 52>;

      #gpio-cells = <2>;

    };

Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml

0 → 100644
+177 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Broadcom BCM6318 GPIO System Controller Device Tree Bindings



maintainers:

  - Álvaro Fernández Rojas <noltari@gmail.com>

  - Jonas Gorski <jonas.gorski@gmail.com>



description:

  Broadcom BCM6318 SoC GPIO system controller which provides a register map

  for controlling the GPIO and pins of the SoC.



properties:

  "#address-cells": true



  "#size-cells": true



  compatible:

    items:

      - const: brcm,bcm6318-gpio-sysctl

      - const: syscon

      - const: simple-mfd



  ranges:

    maxItems: 1



  reg:

    maxItems: 1



patternProperties:

  "^gpio@[0-9a-f]+$":

    # Child node

    type: object

    $ref: "../gpio/brcm,bcm6345-gpio.yaml"

    description:

      GPIO controller for the SoC GPIOs. This child node definition

      should follow the bindings specified in

      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.



  "^pinctrl@[0-9a-f]+$":

    # Child node

    type: object

    $ref: "../pinctrl/brcm,bcm6318-pinctrl.yaml"

    description:

      Pin controller for the SoC pins. This child node definition

      should follow the bindings specified in

      Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml.



required:

  - "#address-cells"

  - compatible

  - ranges

  - reg

  - "#size-cells"



additionalProperties: false



examples:

  - |

    syscon@10000080 {

      #address-cells = <1>;

      #size-cells = <1>;

      compatible = "brcm,bcm6318-gpio-sysctl", "syscon", "simple-mfd";

      reg = <0x10000080 0x80>;

      ranges = <0 0x10000080 0x80>;



      gpio@0 {

        compatible = "brcm,bcm6318-gpio";

        reg-names = "dirout", "dat";

        reg = <0x0 0x8>, <0x8 0x8>;



        gpio-controller;

        gpio-ranges = <&pinctrl 0 0 50>;

        #gpio-cells = <2>;

      };



      pinctrl: pinctrl@10 {

        compatible = "brcm,bcm6318-pinctrl";

        reg = <0x18 0x10>, <0x54 0x18>;



        pinctrl_ephy0_spd_led: ephy0_spd_led-pins {

          function = "ephy0_spd_led";

          pins = "gpio0";

        };



        pinctrl_ephy1_spd_led: ephy1_spd_led-pins {

          function = "ephy1_spd_led";

          pins = "gpio1";

        };



        pinctrl_ephy2_spd_led: ephy2_spd_led-pins {

          function = "ephy2_spd_led";

          pins = "gpio2";

        };



        pinctrl_ephy3_spd_led: ephy3_spd_led-pins {

          function = "ephy3_spd_led";

          pins = "gpio3";

        };



        pinctrl_ephy0_act_led: ephy0_act_led-pins {

          function = "ephy0_act_led";

          pins = "gpio4";

        };



        pinctrl_ephy1_act_led: ephy1_act_led-pins {

          function = "ephy1_act_led";

          pins = "gpio5";

        };



        pinctrl_ephy2_act_led: ephy2_act_led-pins {

          function = "ephy2_act_led";

          pins = "gpio6";

        };



        pinctrl_ephy3_act_led: ephy3_act_led-pins {

          function = "ephy3_act_led";

          pins = "gpio7";

        };



        pinctrl_serial_led: serial_led-pins {

          pinctrl_serial_led_data: serial_led_data-pins {

            function = "serial_led_data";

            pins = "gpio6";

          };



          pinctrl_serial_led_clk: serial_led_clk-pins {

            function = "serial_led_clk";

            pins = "gpio7";

          };

        };



        pinctrl_inet_act_led: inet_act_led-pins {

          function = "inet_act_led";

          pins = "gpio8";

        };



        pinctrl_inet_fail_led: inet_fail_led-pins {

          function = "inet_fail_led";

          pins = "gpio9";

        };



        pinctrl_dsl_led: dsl_led-pins {

          function = "dsl_led";

          pins = "gpio10";

        };



        pinctrl_post_fail_led: post_fail_led-pins {

          function = "post_fail_led";

          pins = "gpio11";

        };



        pinctrl_wlan_wps_led: wlan_wps_led-pins {

          function = "wlan_wps_led";

          pins = "gpio12";

        };



        pinctrl_usb_pwron: usb_pwron-pins {

          function = "usb_pwron";

          pins = "gpio13";

        };



        pinctrl_usb_device_led: usb_device_led-pins {

          function = "usb_device_led";

          pins = "gpio13";

        };



        pinctrl_usb_active: usb_active-pins {

          function = "usb_active";

          pins = "gpio40";

        };

      };

    };

Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml

0 → 100644
+194 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Broadcom BCM63268 GPIO System Controller Device Tree Bindings



maintainers:

  - Álvaro Fernández Rojas <noltari@gmail.com>

  - Jonas Gorski <jonas.gorski@gmail.com>



description:

  Broadcom BCM63268 SoC GPIO system controller which provides a register map

  for controlling the GPIO and pins of the SoC.



properties:

  "#address-cells": true



  "#size-cells": true



  compatible:

    items:

      - const: brcm,bcm63268-gpio-sysctl

      - const: syscon

      - const: simple-mfd



  ranges:

    maxItems: 1



  reg:

    maxItems: 1



patternProperties:

  "^gpio@[0-9a-f]+$":

    # Child node

    type: object

    $ref: "../gpio/brcm,bcm6345-gpio.yaml"

    description:

      GPIO controller for the SoC GPIOs. This child node definition

      should follow the bindings specified in

      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.



  "^pinctrl@[0-9a-f]+$":

    # Child node

    type: object

    $ref: "../pinctrl/brcm,bcm63268-pinctrl.yaml"

    description:

      Pin controller for the SoC pins. This child node definition

      should follow the bindings specified in

      Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml.



required:

  - "#address-cells"

  - compatible

  - ranges

  - reg

  - "#size-cells"



additionalProperties: false



examples:

  - |

    syscon@100000c0 {

      #address-cells = <1>;

      #size-cells = <1>;

      compatible = "brcm,bcm63268-gpio-sysctl", "syscon", "simple-mfd";

      reg = <0x100000c0 0x80>;

      ranges = <0 0x100000c0 0x80>;



      gpio@0 {

        compatible = "brcm,bcm63268-gpio";

        reg-names = "dirout", "dat";

        reg = <0x0 0x8>, <0x8 0x8>;



        gpio-controller;

        gpio-ranges = <&pinctrl 0 0 52>;

        #gpio-cells = <2>;

      };



      pinctrl: pinctrl@10 {

        compatible = "brcm,bcm63268-pinctrl";

        reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;



        pinctrl_serial_led: serial_led-pins {

          pinctrl_serial_led_clk: serial_led_clk-pins {

            function = "serial_led_clk";

            pins = "gpio0";

          };



          pinctrl_serial_led_data: serial_led_data-pins {

            function = "serial_led_data";

            pins = "gpio1";

          };

        };



        pinctrl_hsspi_cs4: hsspi_cs4-pins {

          function = "hsspi_cs4";

          pins = "gpio16";

        };



        pinctrl_hsspi_cs5: hsspi_cs5-pins {

          function = "hsspi_cs5";

          pins = "gpio17";

        };



        pinctrl_hsspi_cs6: hsspi_cs6-pins {

          function = "hsspi_cs6";

          pins = "gpio8";

        };



        pinctrl_hsspi_cs7: hsspi_cs7-pins {

          function = "hsspi_cs7";

          pins = "gpio9";

        };



        pinctrl_adsl_spi: adsl_spi-pins {

          pinctrl_adsl_spi_miso: adsl_spi_miso-pins {

            function = "adsl_spi_miso";

            pins = "gpio18";

          };



          pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {

            function = "adsl_spi_mosi";

            pins = "gpio19";

          };

        };



        pinctrl_vreq_clk: vreq_clk-pins {

          function = "vreq_clk";

          pins = "gpio22";

        };



        pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {

          function = "pcie_clkreq_b";

          pins = "gpio23";

        };



        pinctrl_robosw_led_clk: robosw_led_clk-pins {

          function = "robosw_led_clk";

          pins = "gpio30";

        };



        pinctrl_robosw_led_data: robosw_led_data-pins {

          function = "robosw_led_data";

          pins = "gpio31";

        };



        pinctrl_nand: nand-pins {

          function = "nand";

          group = "nand_grp";

        };



        pinctrl_gpio35_alt: gpio35_alt-pins {

          function = "gpio35_alt";

          pin = "gpio35";

        };



        pinctrl_dectpd: dectpd-pins {

          function = "dectpd";

          group = "dectpd_grp";

        };



        pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {

          function = "vdsl_phy_override_0";

          group = "vdsl_phy_override_0_grp";

        };



        pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {

          function = "vdsl_phy_override_1";

          group = "vdsl_phy_override_1_grp";

        };



        pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {

          function = "vdsl_phy_override_2";

          group = "vdsl_phy_override_2_grp";

        };



        pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {

          function = "vdsl_phy_override_3";

          group = "vdsl_phy_override_3_grp";

        };



        pinctrl_dsl_gpio8: dsl_gpio8-pins {

          function = "dsl_gpio8";

          group = "dsl_gpio8";

        };



        pinctrl_dsl_gpio9: dsl_gpio9-pins {

          function = "dsl_gpio9";

          group = "dsl_gpio9";

        };

      };

    };