Commit 65c0c236 authored by Zhang Rui's avatar Zhang Rui Committed by Rafael J. Wysocki
Browse files

intel_idle: Add AlderLake-N support 



Similar to the other other AlderLake platforms, the C1 and C1E states on
ADL-N are mutually exclusive. Only one of them can be enabled at a time.

C1E is preferred on ADL-N for better energy efficiency.

C6S is also supported on this platform. Its latency is far bigger than
C6, but really close to C8 (PC8), thus it is not exposed as a separate
state.

Suggested-by: default avatarBaieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Suggested-by: default avatarVinay Kumar <vinay.kumar@intel.com>
Signed-off-by: default avatarZhang Rui <rui.zhang@intel.com>
[ rjw: Changelog edits ]
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 06f7c087

drivers/idle/intel_idle.c

+51 −0
Original line number Diff line number Diff line
@@ -928,6 +928,51 @@ static struct cpuidle_state adl_l_cstates[] __initdata = { 
		.enter = NULL }

};



static struct cpuidle_state adl_n_cstates[] __initdata = {

	{

		.name = "C1",

		.desc = "MWAIT 0x00",

		.flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE,

		.exit_latency = 1,

		.target_residency = 1,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C1E",

		.desc = "MWAIT 0x01",

		.flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,

		.exit_latency = 2,

		.target_residency = 4,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C6",

		.desc = "MWAIT 0x20",

		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 195,

		.target_residency = 585,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C8",

		.desc = "MWAIT 0x40",

		.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 260,

		.target_residency = 1040,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.name = "C10",

		.desc = "MWAIT 0x60",

		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 660,

		.target_residency = 1980,

		.enter = &intel_idle,

		.enter_s2idle = intel_idle_s2idle, },

	{

		.enter = NULL }

};



static struct cpuidle_state spr_cstates[] __initdata = {

	{

		.name = "C1",
@@ -1309,6 +1354,10 @@ static const struct idle_cpu idle_cpu_adl_l __initconst = { 
	.state_table = adl_l_cstates,

};



static const struct idle_cpu idle_cpu_adl_n __initconst = {

	.state_table = adl_n_cstates,

};



static const struct idle_cpu idle_cpu_spr __initconst = {

	.state_table = spr_cstates,

	.disable_promotion_to_c1e = true,
@@ -1379,6 +1428,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,		&idle_cpu_icx),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&idle_cpu_adl),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&idle_cpu_adl_l),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,		&idle_cpu_adl_n),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&idle_cpu_spr),

	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL,	&idle_cpu_knl),

	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM,	&idle_cpu_knl),
@@ -1816,6 +1866,7 @@ static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv) 
		break;

	case INTEL_FAM6_ALDERLAKE:

	case INTEL_FAM6_ALDERLAKE_L:

	case INTEL_FAM6_ALDERLAKE_N:

		adl_idle_state_table_update();

		break;

	}