Commit 65bf1fbe authored by Sam Protsenko's avatar Sam Protsenko Committed by Krzysztof Kozlowski
Browse files

clk: samsung: Don't pass reg_base to samsung_clk_register_pll() 



Base address can be derived from context structure. Remove `base'
argument from samsung_clk_register_pll() and use `ctx->reg_base'
instead, as it's done in other clock registering functions.

No functional change.

Acked-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Tested-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223041938.22732-2-semen.protsenko@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 45dab818

drivers/clk/samsung/clk-exynos4.c

+2 −2
Original line number Diff line number Diff line
@@ -1276,7 +1276,7 @@ static void __init exynos4_clk_init(struct device_node *np, 
							exynos4210_vpll_rates;



		samsung_clk_register_pll(ctx, exynos4210_plls,

					ARRAY_SIZE(exynos4210_plls), reg_base);

					ARRAY_SIZE(exynos4210_plls));

	} else {

		if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {

			exynos4x12_plls[apll].rate_table =
@@ -1288,7 +1288,7 @@ static void __init exynos4_clk_init(struct device_node *np, 
		}



		samsung_clk_register_pll(ctx, exynos4x12_plls,

					ARRAY_SIZE(exynos4x12_plls), reg_base);

					ARRAY_SIZE(exynos4x12_plls));

	}



	samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,

drivers/clk/samsung/clk-exynos5250.c

+1 −2
Original line number Diff line number Diff line
@@ -815,8 +815,7 @@ static void __init exynos5250_clk_init(struct device_node *np) 
		exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;



	samsung_clk_register_pll(ctx, exynos5250_plls,

			ARRAY_SIZE(exynos5250_plls),

			reg_base);

			ARRAY_SIZE(exynos5250_plls));

	samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,

			ARRAY_SIZE(exynos5250_fixed_rate_clks));

	samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,

drivers/clk/samsung/clk-exynos5420.c

+1 −2
Original line number Diff line number Diff line
@@ -1606,8 +1606,7 @@ static void __init exynos5x_clk_init(struct device_node *np, 
	else

		exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;



	samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),

					reg_base);

	samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls));

	samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,

			ARRAY_SIZE(exynos5x_fixed_rate_clks));

	samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,

drivers/clk/samsung/clk-exynos5433.c

+2 −2
Original line number Diff line number Diff line
@@ -5610,8 +5610,8 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev) 
	pm_runtime_enable(dev);



	if (info->pll_clks)

		samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks,

					 reg_base);

		samsung_clk_register_pll(ctx, info->pll_clks,

					 info->nr_pll_clks);

	if (info->mux_clks)

		samsung_clk_register_mux(ctx, info->mux_clks,

					 info->nr_mux_clks);

drivers/clk/samsung/clk-pll.c

+5 −6
Original line number Diff line number Diff line
@@ -1259,8 +1259,7 @@ static const struct clk_ops samsung_pll2650xx_clk_min_ops = { 
};



static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,

				const struct samsung_pll_clock *pll_clk,

				void __iomem *base)

				const struct samsung_pll_clock *pll_clk)

{

	struct samsung_clk_pll *pll;

	struct clk_init_data init;
@@ -1395,8 +1394,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, 


	pll->hw.init = &init;

	pll->type = pll_clk->type;

	pll->lock_reg = base + pll_clk->lock_offset;

	pll->con_reg = base + pll_clk->con_offset;

	pll->lock_reg = ctx->reg_base + pll_clk->lock_offset;

	pll->con_reg = ctx->reg_base + pll_clk->con_offset;



	ret = clk_hw_register(ctx->dev, &pll->hw);

	if (ret) {
@@ -1412,10 +1411,10 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, 


void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,

			const struct samsung_pll_clock *pll_list,

			unsigned int nr_pll, void __iomem *base)

			unsigned int nr_pll)

{

	int cnt;



	for (cnt = 0; cnt < nr_pll; cnt++)

		_samsung_clk_register_pll(ctx, &pll_list[cnt], base);

		_samsung_clk_register_pll(ctx, &pll_list[cnt]);

}