Commit 65b0c564 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

clk: qcom: rpmh: reuse common duplicate clocks 



After the grouping it is obvious that some of the clock definitions are
pure duplicates. Rename them to use a single common name for the clock.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarBjorn Andersson <andersson@kernel.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221202185843.721673-3-dmitry.baryshkov@linaro.org
parent 82349cc0

drivers/clk/qcom/clk-rpmh.c

+9 −15
Original line number Diff line number Diff line
@@ -350,9 +350,7 @@ DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4); 
DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);

DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);

DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);

DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);



DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);

DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);

DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4);
@@ -362,7 +360,6 @@ DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4); 
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);

DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);

DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);

DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);

DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1);

DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1);
@@ -370,14 +367,11 @@ DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1); 
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1);

DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1);

DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1);

DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1);

DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1);



DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2);



DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");

DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0");

DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0");

DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0");

DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0");

DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0");
@@ -427,12 +421,12 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = { 
static struct clk_hw *sdx55_rpmh_clocks[] = {

	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,

	[RPMH_CXO_CLK_A]	= &sdm845_bi_tcxo_ao.hw,

	[RPMH_RF_CLK1]		= &sdx55_rf_clk1.hw,

	[RPMH_RF_CLK1_A]	= &sdx55_rf_clk1_ao.hw,

	[RPMH_RF_CLK2]		= &sdx55_rf_clk2.hw,

	[RPMH_RF_CLK2_A]	= &sdx55_rf_clk2_ao.hw,

	[RPMH_RF_CLK1]		= &sc8180x_rf_clk1.hw,

	[RPMH_RF_CLK1_A]	= &sc8180x_rf_clk1_ao.hw,

	[RPMH_RF_CLK2]		= &sc8180x_rf_clk2.hw,

	[RPMH_RF_CLK2_A]	= &sc8180x_rf_clk2_ao.hw,

	[RPMH_QPIC_CLK]		= &sdx55_qpic_clk.hw,

	[RPMH_IPA_CLK]		= &sdx55_ipa.hw,

	[RPMH_IPA_CLK]		= &sdm845_ipa.hw,

};



static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
@@ -549,8 +543,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = { 
static struct clk_hw *sc8280xp_rpmh_clocks[] = {

	[RPMH_CXO_CLK]		= &sdm845_bi_tcxo.hw,

	[RPMH_CXO_CLK_A]	= &sdm845_bi_tcxo_ao.hw,

	[RPMH_LN_BB_CLK3]       = &sc8280xp_ln_bb_clk3.hw,

	[RPMH_LN_BB_CLK3_A]     = &sc8280xp_ln_bb_clk3_ao.hw,

	[RPMH_LN_BB_CLK3]       = &sdm845_ln_bb_clk3.hw,

	[RPMH_LN_BB_CLK3_A]     = &sdm845_ln_bb_clk3_ao.hw,

	[RPMH_IPA_CLK]          = &sdm845_ipa.hw,

	[RPMH_PKA_CLK]          = &sm8350_pka.hw,

	[RPMH_HWKM_CLK]         = &sm8350_hwkm.hw,
@@ -624,8 +618,8 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = { 
static struct clk_hw *sdx65_rpmh_clocks[] = {

	[RPMH_CXO_CLK]          = &sc7280_bi_tcxo.hw,

	[RPMH_CXO_CLK_A]        = &sc7280_bi_tcxo_ao.hw,

	[RPMH_LN_BB_CLK1]       = &sdx65_ln_bb_clk1.hw,

	[RPMH_LN_BB_CLK1_A]     = &sdx65_ln_bb_clk1_ao.hw,

	[RPMH_LN_BB_CLK1]       = &sm8450_ln_bb_clk1.hw,

	[RPMH_LN_BB_CLK1_A]     = &sm8450_ln_bb_clk1_ao.hw,

	[RPMH_RF_CLK1]          = &sdm845_rf_clk1.hw,

	[RPMH_RF_CLK1_A]        = &sdm845_rf_clk1_ao.hw,

	[RPMH_RF_CLK2]          = &sdm845_rf_clk2.hw,