Commit 65ace9a8 authored by qizhong cheng's avatar qizhong cheng Committed by Lorenzo Pieralisi
Browse files

PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize 

Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
be delayed 100ms (TPVPERL) for the power and clock to become stable.

Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com


Signed-off-by: default avatarqizhong cheng <qizhong.cheng@mediatek.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarPali Rohár <pali@kernel.org>
parent fa55b7dc

drivers/pci/controller/pcie-mediatek.c

+7 −0
Original line number Diff line number Diff line
@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 
	 */

	writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);



	/*

	 * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and

	 * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should

	 * be delayed 100ms (TPVPERL) for the power and clock to become stable.

	 */

	msleep(100);



	/* De-assert PHY, PE, PIPE, MAC and configuration reset	*/

	val = readl(port->base + PCIE_RST_CTRL);

	val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |