Commit 65a2c14d authored by Nobuhiro Iwamatsu's avatar Nobuhiro Iwamatsu Committed by Greg Kroah-Hartman
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dt-bindings: serial: convert Cadence UART bindings to YAML



Convert serial for Cadence UART bindings documentation to YAML.

Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Link: https://lore.kernel.org/r/20210715092252.225740-1-iwamatsu@nigauri.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 5bbe10a6
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Binding for Cadence UART Controller

Required properties:
- compatible :
  Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
  Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
- reg: Should contain UART controller registers location and length.
- interrupts: Should contain UART controller interrupts.
- clocks: Must contain phandles to the UART clocks
  See ../clocks/clock-bindings.txt for details.
- clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk"
  See ../clocks/clock-bindings.txt for details.


Optional properties:
- cts-override : Override the CTS modem status signal. This signal will
  always be reported as active instead of being obtained from the modem status
  register. Define this if your serial port does not use this pin

Example:
	uart@e0000000 {
		compatible = "cdns,uart-r1p8";
		clocks = <&clkc 23>, <&clkc 40>;
		clock-names = "uart_clk", "pclk";
		reg = <0xE0000000 0x1000>;
		interrupts = <0 27 4>;
	};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence UART Controller Device Tree Bindings

maintainers:
  - Michal Simek <michal.simek@xilinx.com>

allOf:
  - $ref: /schemas/serial.yaml#

properties:
  compatible:
    oneOf:
      - description: UART controller for Zynq-7xxx SoC
        items:
          - const: xlnx,xuartps
          - const: cdns,uart-r1p8
      - description: UART controller for Zynq Ultrascale+ MPSoC
        items:
          - const: xlnx,zynqmp-uart
          - const: cdns,uart-r1p12

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: uart_clk
      - const: pclk

  cts-override:
    description: |
      Override the CTS modem status signal. This signal will
      always be reported as active instead of being obtained
      from the modem status register. Define this if your serial
      port does not use this pin.
    type: boolean

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    uart0: serial@e0000000 {
      compatible = "xlnx,xuartps", "cdns,uart-r1p8";
      clocks = <&clkc 23>, <&clkc 40>;
      clock-names = "uart_clk", "pclk";
      reg = <0xE0000000 0x1000>;
      interrupts = <0 27 4>;
    };