Commit 6575eb93 authored by Tim Huang's avatar Tim Huang Committed by Alex Deucher
Browse files

drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.0 



Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro
definitions for AMD_CG_SUPPORT_BIF_LS.

Signed-off-by: default avatarTim Huang <tim.huang@amd.com>
Reviewed-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d6c770d2

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h

+2 −0
Original line number Diff line number Diff line
@@ -15243,6 +15243,8 @@ 
#define regBIF0_PCIE_TX_TRACKING_ADDR_HI_BASE_IDX                                                       5

#define regBIF0_PCIE_TX_TRACKING_CTRL_STATUS                                                            0x420186

#define regBIF0_PCIE_TX_TRACKING_CTRL_STATUS_BASE_IDX                                                   5

#define regBIF0_PCIE_TX_POWER_CTRL_1                                                                    0x420187

#define regBIF0_PCIE_TX_POWER_CTRL_1_BASE_IDX                                                           5

#define regBIF0_PCIE_TX_CTRL_4                                                                          0x42018b

#define regBIF0_PCIE_TX_CTRL_4_BASE_IDX                                                                 5

#define regBIF0_PCIE_TX_STATUS                                                                          0x420194

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h

+13 −0
Original line number Diff line number Diff line
@@ -85627,6 +85627,19 @@ 
#define BIF0_PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK                                              0x0000000EL

#define BIF0_PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK                                           0x00007F00L

#define BIF0_PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK                                      0x00008000L

//BIF0_PCIE_TX_POWER_CTRL_1

#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN__SHIFT                                                       0x0

#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_DS_EN__SHIFT                                                       0x1

#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_SD_EN__SHIFT                                                       0x2

#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN__SHIFT                                                    0x3

#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_DS_EN__SHIFT                                                    0x4

#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_SD_EN__SHIFT                                                    0x5

#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK                                                         0x00000001L

#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_DS_EN_MASK                                                         0x00000002L

#define BIF0_PCIE_TX_POWER_CTRL_1__MST_MEM_SD_EN_MASK                                                         0x00000004L

#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK                                                      0x00000008L

#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_DS_EN_MASK                                                      0x00000010L

#define BIF0_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_SD_EN_MASK                                                      0x00000020L

//BIF0_PCIE_TX_CTRL_4

#define BIF0_PCIE_TX_CTRL_4__TX_PORT_ACCESS_TIMER_SKEW__SHIFT                                                 0x0

#define BIF0_PCIE_TX_CTRL_4__TX_PORT_ACCESS_TIMER_SKEW_MASK                                                   0x0000000FL