Loading drivers/pci/host/pcie-designware.c +5 −5 Original line number Diff line number Diff line Loading @@ -807,11 +807,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val; /* get iATU unroll support */ pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp); dev_dbg(pp->dev, "iATU unroll: %s\n", pp->iatu_unroll_enabled ? "enabled" : "disabled"); /* set the number of lanes */ val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL); val &= ~PORT_LINK_MODE_MASK; Loading Loading @@ -882,6 +877,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * we should not program the ATU here. */ if (!pp->ops->rd_other_conf) { /* get iATU unroll support */ pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp); dev_dbg(pp->dev, "iATU unroll: %s\n", pp->iatu_unroll_enabled ? "enabled" : "disabled"); dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size); Loading Loading
drivers/pci/host/pcie-designware.c +5 −5 Original line number Diff line number Diff line Loading @@ -807,11 +807,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val; /* get iATU unroll support */ pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp); dev_dbg(pp->dev, "iATU unroll: %s\n", pp->iatu_unroll_enabled ? "enabled" : "disabled"); /* set the number of lanes */ val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL); val &= ~PORT_LINK_MODE_MASK; Loading Loading @@ -882,6 +877,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * we should not program the ATU here. */ if (!pp->ops->rd_other_conf) { /* get iATU unroll support */ pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp); dev_dbg(pp->dev, "iATU unroll: %s\n", pp->iatu_unroll_enabled ? "enabled" : "disabled"); dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size); Loading