Commit 6541b424 authored by Finley Xiao's avatar Finley Xiao Committed by Heiko Stuebner
Browse files

soc: rockchip: power-domain: add power domain support for rk3588 



This driver is modified to support RK3588 SoCs.

Signed-off-by: default avatarFinley Xiao <finley.xiao@rock-chips.com>
[port of downstream code incl. merging in fixes]
Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20220906143825.199089-7-sebastian.reichel@collabora.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 47bceb7c

drivers/soc/rockchip/pm_domains.c

+87 −4
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include <dt-bindings/power/rk3368-power.h>

#include <dt-bindings/power/rk3399-power.h>

#include <dt-bindings/power/rk3568-power.h>

#include <dt-bindings/power/rk3588-power.h>



struct rockchip_domain_info {

	const char *name;
@@ -42,6 +43,9 @@ struct rockchip_domain_info { 
	bool active_wakeup;

	int pwr_w_mask;

	int req_w_mask;

	int repair_status_mask;

	u32 pwr_offset;

	u32 req_offset;

};



struct rockchip_pmu_info {
@@ -50,6 +54,7 @@ struct rockchip_pmu_info { 
	u32 req_offset;

	u32 idle_offset;

	u32 ack_offset;

	u32 repair_status_offset;



	u32 core_pwrcnt_offset;

	u32 gpu_pwrcnt_offset;
@@ -114,6 +119,22 @@ struct rockchip_pmu { 
	.active_wakeup = wakeup,			\

}



#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup)	\

{							\

	.name = _name,					\

	.pwr_offset = p_offset,				\

	.pwr_w_mask = (pwr) << 16,			\

	.pwr_mask = (pwr),				\

	.status_mask = (status),			\

	.repair_status_mask = (r_status),		\

	.req_offset = r_offset,				\

	.req_w_mask = (req) << 16,			\

	.req_mask = (req),				\

	.idle_mask = (idle),				\

	.ack_mask = (ack),				\

	.active_wakeup = wakeup,			\

}



#define DOMAIN_RK3036(_name, req, ack, idle, wakeup)		\

{							\

	.name = _name,				\
@@ -248,6 +269,9 @@ void rockchip_pmu_unblock(void) 
}

EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);



#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup)	\

	DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup)



static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)

{

	struct rockchip_pmu *pmu = pd->pmu;
@@ -272,6 +296,7 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, 
	const struct rockchip_domain_info *pd_info = pd->info;

	struct generic_pm_domain *genpd = &pd->genpd;

	struct rockchip_pmu *pmu = pd->pmu;

	u32 pd_req_offset = pd_info->req_offset;

	unsigned int target_ack;

	unsigned int val;

	bool is_idle;
@@ -280,11 +305,11 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, 
	if (pd_info->req_mask == 0)

		return 0;

	else if (pd_info->req_w_mask)

		regmap_write(pmu->regmap, pmu->info->req_offset,

		regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset,

			     idle ? (pd_info->req_mask | pd_info->req_w_mask) :

			     pd_info->req_w_mask);

	else

		regmap_update_bits(pmu->regmap, pmu->info->req_offset,

		regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset,

				   pd_info->req_mask, idle ? -1U : 0);



	wmb();
@@ -367,6 +392,12 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd) 
	struct rockchip_pmu *pmu = pd->pmu;

	unsigned int val;



	if (pd->info->repair_status_mask) {

		regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);

		/* 1'b1: power on, 1'b0: power off */

		return val & pd->info->repair_status_mask;

	}



	/* check idle status for idle-only domains */

	if (pd->info->status_mask == 0)

		return !rockchip_pmu_domain_is_idle(pd);
@@ -382,16 +413,17 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, 
{

	struct rockchip_pmu *pmu = pd->pmu;

	struct generic_pm_domain *genpd = &pd->genpd;

	u32 pd_pwr_offset = pd->info->pwr_offset;

	bool is_on;



	if (pd->info->pwr_mask == 0)

		return;

	else if (pd->info->pwr_w_mask)

		regmap_write(pmu->regmap, pmu->info->pwr_offset,

		regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,

			     on ? pd->info->pwr_w_mask :

			     (pd->info->pwr_mask | pd->info->pwr_w_mask));

	else

		regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,

		regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,

				   pd->info->pwr_mask, on ? 0 : -1U);



	wmb();
@@ -518,6 +550,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, 
			node, id);

		return -EINVAL;

	}

	/* RK3588 has domains with two parents (RKVDEC0/RKVDEC1) */

	if (pmu->genpd_data.domains[id])

		return 0;



	pd_info = &pmu->info->domain_info[id];

	if (!pd_info) {
@@ -988,6 +1023,38 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = { 
	[RK3568_PD_PIPE]	= DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),

};



static const struct rockchip_domain_info rk3588_pm_domains[] = {

	[RK3588_PD_GPU]		= DOMAIN_RK3588("gpu",     0x0, BIT(0),  0,       BIT(1),  0x0, BIT(0),  BIT(0),  false),

	[RK3588_PD_NPU]		= DOMAIN_RK3588("npu",     0x0, BIT(1),  BIT(1),  0,       0x0, 0,       0,       false),

	[RK3588_PD_VCODEC]	= DOMAIN_RK3588("vcodec",  0x0, BIT(2),  BIT(2),  0,       0x0, 0,       0,       false),

	[RK3588_PD_NPUTOP]	= DOMAIN_RK3588("nputop",  0x0, BIT(3),  0,       BIT(2),  0x0, BIT(1),  BIT(1),  false),

	[RK3588_PD_NPU1]	= DOMAIN_RK3588("npu1",    0x0, BIT(4),  0,       BIT(3),  0x0, BIT(2),  BIT(2),  false),

	[RK3588_PD_NPU2]	= DOMAIN_RK3588("npu2",    0x0, BIT(5),  0,       BIT(4),  0x0, BIT(3),  BIT(3),  false),

	[RK3588_PD_VENC0]	= DOMAIN_RK3588("venc0",   0x0, BIT(6),  0,       BIT(5),  0x0, BIT(4),  BIT(4),  false),

	[RK3588_PD_VENC1]	= DOMAIN_RK3588("venc1",   0x0, BIT(7),  0,       BIT(6),  0x0, BIT(5),  BIT(5),  false),

	[RK3588_PD_RKVDEC0]	= DOMAIN_RK3588("rkvdec0", 0x0, BIT(8),  0,       BIT(7),  0x0, BIT(6),  BIT(6),  false),

	[RK3588_PD_RKVDEC1]	= DOMAIN_RK3588("rkvdec1", 0x0, BIT(9),  0,       BIT(8),  0x0, BIT(7),  BIT(7),  false),

	[RK3588_PD_VDPU]	= DOMAIN_RK3588("vdpu",    0x0, BIT(10), 0,       BIT(9),  0x0, BIT(8),  BIT(8),  false),

	[RK3588_PD_RGA30]	= DOMAIN_RK3588("rga30",   0x0, BIT(11), 0,       BIT(10), 0x0, 0,       0,       false),

	[RK3588_PD_AV1]		= DOMAIN_RK3588("av1",     0x0, BIT(12), 0,       BIT(11), 0x0, BIT(9),  BIT(9),  false),

	[RK3588_PD_VI]		= DOMAIN_RK3588("vi",      0x0, BIT(13), 0,       BIT(12), 0x0, BIT(10), BIT(10), false),

	[RK3588_PD_FEC]		= DOMAIN_RK3588("fec",     0x0, BIT(14), 0,       BIT(13), 0x0, 0,       0,       false),

	[RK3588_PD_ISP1]	= DOMAIN_RK3588("isp1",    0x0, BIT(15), 0,       BIT(14), 0x0, BIT(11), BIT(11), false),

	[RK3588_PD_RGA31]	= DOMAIN_RK3588("rga31",   0x4, BIT(0),  0,       BIT(15), 0x0, BIT(12), BIT(12), false),

	[RK3588_PD_VOP]		= DOMAIN_RK3588("vop",     0x4, BIT(1),  0,       BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),

	[RK3588_PD_VO0]		= DOMAIN_RK3588("vo0",     0x4, BIT(2),  0,       BIT(17), 0x0, BIT(15), BIT(15), false),

	[RK3588_PD_VO1]		= DOMAIN_RK3588("vo1",     0x4, BIT(3),  0,       BIT(18), 0x4, BIT(0),  BIT(16), false),

	[RK3588_PD_AUDIO]	= DOMAIN_RK3588("audio",   0x4, BIT(4),  0,       BIT(19), 0x4, BIT(1),  BIT(17), false),

	[RK3588_PD_PHP]		= DOMAIN_RK3588("php",     0x4, BIT(5),  0,       BIT(20), 0x4, BIT(5),  BIT(21), false),

	[RK3588_PD_GMAC]	= DOMAIN_RK3588("gmac",    0x4, BIT(6),  0,       BIT(21), 0x0, 0,       0,       false),

	[RK3588_PD_PCIE]	= DOMAIN_RK3588("pcie",    0x4, BIT(7),  0,       BIT(22), 0x0, 0,       0,       true),

	[RK3588_PD_NVM]		= DOMAIN_RK3588("nvm",     0x4, BIT(8),  BIT(24), 0,       0x4, BIT(2),  BIT(18), false),

	[RK3588_PD_NVM0]	= DOMAIN_RK3588("nvm0",    0x4, BIT(9),  0,       BIT(23), 0x0, 0,       0,       false),

	[RK3588_PD_SDIO]	= DOMAIN_RK3588("sdio",    0x4, BIT(10), 0,       BIT(24), 0x4, BIT(3),  BIT(19), false),

	[RK3588_PD_USB]		= DOMAIN_RK3588("usb",     0x4, BIT(11), 0,       BIT(25), 0x4, BIT(4),  BIT(20), true),

	[RK3588_PD_SDMMC]	= DOMAIN_RK3588("sdmmc",   0x4, BIT(13), 0,       BIT(26), 0x0, 0,       0,       false),

};



static const struct rockchip_pmu_info px30_pmu = {

	.pwr_offset = 0x18,

	.status_offset = 0x20,
@@ -1134,6 +1201,18 @@ static const struct rockchip_pmu_info rk3568_pmu = { 
	.domain_info = rk3568_pm_domains,

};



static const struct rockchip_pmu_info rk3588_pmu = {

	.pwr_offset = 0x14c,

	.status_offset = 0x180,

	.req_offset = 0x10c,

	.idle_offset = 0x120,

	.ack_offset = 0x118,

	.repair_status_offset = 0x290,



	.num_domains = ARRAY_SIZE(rk3588_pm_domains),

	.domain_info = rk3588_pm_domains,

};



static const struct rockchip_pmu_info rv1126_pmu = {

	.pwr_offset = 0x110,

	.status_offset = 0x108,
@@ -1194,6 +1273,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { 
		.compatible = "rockchip,rk3568-power-controller",

		.data = (void *)&rk3568_pmu,

	},

	{

		.compatible = "rockchip,rk3588-power-controller",

		.data = (void *)&rk3588_pmu,

	},

	{

		.compatible = "rockchip,rv1126-power-controller",

		.data = (void *)&rv1126_pmu,