Commit 651e7d48 authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915: replace IS_GEN and friends with GRAPHICS_VER 



This was done by the following semantic patch:

	@@ expression i915; @@
	- INTEL_GEN(i915)
	+ GRAPHICS_VER(i915)

	@@ expression i915; expression E; @@
	- INTEL_GEN(i915) >= E
	+ GRAPHICS_VER(i915) >= E

	@@ expression dev_priv; expression E; @@
	- !IS_GEN(dev_priv, E)
	+ GRAPHICS_VER(dev_priv) != E

	@@ expression dev_priv; expression E; @@
	- IS_GEN(dev_priv, E)
	+ GRAPHICS_VER(dev_priv) == E

	@@
	expression dev_priv;
	expression from, until;
	@@
	- IS_GEN_RANGE(dev_priv, from, until)
	+ IS_GRAPHICS_VER(dev_priv, from, until)

	@def@
	expression E;
	identifier id =~ "^gen$";
	@@
	- id = GRAPHICS_VER(E)
	+ ver = GRAPHICS_VER(E)

	@@
	identifier def.id;
	@@
	- id
	+ ver

It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".

Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210606045050.103862-2-lucas.demarchi@intel.com
parent 07960a4c

drivers/gpu/drm/i915/i915_cmd_parser.c

+5 −5
Original line number Diff line number Diff line
@@ -946,7 +946,7 @@ int intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 
	int cmd_table_count;

	int ret;



	if (!IS_GEN(engine->i915, 7) && !(IS_GEN(engine->i915, 9) &&

	if (GRAPHICS_VER(engine->i915) != 7 && !(GRAPHICS_VER(engine->i915) == 9 &&

						 engine->class == COPY_ENGINE_CLASS))

		return 0;
@@ -977,7 +977,7 @@ int intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 
		break;

	case COPY_ENGINE_CLASS:

		engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;

		if (IS_GEN(engine->i915, 9)) {

		if (GRAPHICS_VER(engine->i915) == 9) {

			cmd_tables = gen9_blt_cmd_table;

			cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table);

			engine->get_cmd_length_mask =
@@ -993,7 +993,7 @@ int intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 
			cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table);

		}



		if (IS_GEN(engine->i915, 9)) {

		if (GRAPHICS_VER(engine->i915) == 9) {

			engine->reg_tables = gen9_blt_reg_tables;

			engine->reg_table_count =

				ARRAY_SIZE(gen9_blt_reg_tables);
@@ -1521,7 +1521,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, 
				if (IS_HASWELL(engine->i915))

					flags = MI_BATCH_NON_SECURE_HSW;



				GEM_BUG_ON(!IS_GEN_RANGE(engine->i915, 6, 7));

				GEM_BUG_ON(!IS_GRAPHICS_VER(engine->i915, 6, 7));

				__gen6_emit_bb_start(batch_end,

						     batch_addr,

						     flags);

drivers/gpu/drm/i915/i915_debugfs.c

+15 −15
Original line number Diff line number Diff line
@@ -361,7 +361,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 


	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);



	if (IS_GEN(dev_priv, 5)) {

	if (GRAPHICS_VER(dev_priv) == 5) {

		u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);

		u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
@@ -408,7 +408,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		seq_printf(m,

			   "efficient (RPe) frequency: %d MHz\n",

			   intel_gpu_freq(rps, rps->efficient_freq));

	} else if (INTEL_GEN(dev_priv) >= 6) {

	} else if (GRAPHICS_VER(dev_priv) >= 6) {

		u32 rp_state_limits;

		u32 gt_perf_status;

		u32 rp_state_cap;
@@ -432,7 +432,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);



		reqf = intel_uncore_read(&dev_priv->uncore, GEN6_RPNSWREQ);

		if (INTEL_GEN(dev_priv) >= 9)

		if (GRAPHICS_VER(dev_priv) >= 9)

			reqf >>= 23;

		else {

			reqf &= ~GEN6_TURBO_DISABLE;
@@ -458,7 +458,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 


		intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);



		if (INTEL_GEN(dev_priv) >= 11) {

		if (GRAPHICS_VER(dev_priv) >= 11) {

			pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);

			pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);

			/*
@@ -467,7 +467,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
			 */

			pm_isr = 0;

			pm_iir = 0;

		} else if (INTEL_GEN(dev_priv) >= 8) {

		} else if (GRAPHICS_VER(dev_priv) >= 8) {

			pm_ier = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(2));

			pm_imr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(2));

			pm_isr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_ISR(2));
@@ -490,14 +490,14 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 


		seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",

			   pm_ier, pm_imr, pm_mask);

		if (INTEL_GEN(dev_priv) <= 10)

		if (GRAPHICS_VER(dev_priv) <= 10)

			seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",

				   pm_isr, pm_iir);

		seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",

			   rps->pm_intrmsk_mbz);

		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);

		seq_printf(m, "Render p-state ratio: %d\n",

			   (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);

			   (gt_perf_status & (GRAPHICS_VER(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);

		seq_printf(m, "Render p-state VID: %d\n",

			   gt_perf_status & 0xff);

		seq_printf(m, "Render p-state limit: %d\n",
@@ -538,20 +538,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :

			    rp_state_cap >> 16) & 0xff;

		max_freq *= (IS_GEN9_BC(dev_priv) ||

			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",

			   intel_gpu_freq(rps, max_freq));



		max_freq = (rp_state_cap & 0xff00) >> 8;

		max_freq *= (IS_GEN9_BC(dev_priv) ||

			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",

			   intel_gpu_freq(rps, max_freq));



		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :

			    rp_state_cap >> 0) & 0xff;

		max_freq *= (IS_GEN9_BC(dev_priv) ||

			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

			     GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);

		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",

			   intel_gpu_freq(rps, max_freq));

		seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -622,12 +622,12 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 
		seq_puts(m, "L-shaped memory detected\n");



	/* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */

	if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))

	if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))

		return 0;



	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);



	if (IS_GEN_RANGE(dev_priv, 3, 4)) {

	if (IS_GRAPHICS_VER(dev_priv, 3, 4)) {

		seq_printf(m, "DDC = 0x%08x\n",

			   intel_uncore_read(uncore, DCC));

		seq_printf(m, "DDC2 = 0x%08x\n",
@@ -645,7 +645,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 
			   intel_uncore_read(uncore, MAD_DIMM_C2));

		seq_printf(m, "TILECTL = 0x%08x\n",

			   intel_uncore_read(uncore, TILECTL));

		if (INTEL_GEN(dev_priv) >= 8)

		if (GRAPHICS_VER(dev_priv) >= 8)

			seq_printf(m, "GAMTARBMODE = 0x%08x\n",

				   intel_uncore_read(uncore, GAMTARBMODE));

		else
@@ -956,7 +956,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) 


	atomic_inc(&gt->user_wakeref);

	intel_gt_pm_get(gt);

	if (INTEL_GEN(i915) >= 6)

	if (GRAPHICS_VER(i915) >= 6)

		intel_uncore_forcewake_user_get(gt->uncore);



	return 0;
@@ -967,7 +967,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) 
	struct drm_i915_private *i915 = inode->i_private;

	struct intel_gt *gt = &i915->gt;



	if (INTEL_GEN(i915) >= 6)

	if (GRAPHICS_VER(i915) >= 6)

		intel_uncore_forcewake_user_put(&i915->uncore);

	intel_gt_pm_put(gt);

	atomic_dec(&gt->user_wakeref);

drivers/gpu/drm/i915/i915_drv.c

+10 −10
Original line number Diff line number Diff line
@@ -106,12 +106,12 @@ static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) 
static int

intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)

{

	int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp_lo, temp_hi = 0;

	u64 mchbar_addr;

	int ret;



	if (INTEL_GEN(dev_priv) >= 4)

	if (GRAPHICS_VER(dev_priv) >= 4)

		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);

	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);

	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
@@ -138,7 +138,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) 
		return ret;

	}



	if (INTEL_GEN(dev_priv) >= 4)

	if (GRAPHICS_VER(dev_priv) >= 4)

		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,

				       upper_32_bits(dev_priv->mch_res.start));
@@ -151,7 +151,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) 
static void

intel_setup_mchbar(struct drm_i915_private *dev_priv)

{

	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp;

	bool enabled;
@@ -190,7 +190,7 @@ intel_setup_mchbar(struct drm_i915_private *dev_priv) 
static void

intel_teardown_mchbar(struct drm_i915_private *dev_priv)

{

	int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;



	if (dev_priv->mchbar_need_disable) {

		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
@@ -475,7 +475,7 @@ static int i915_set_dma_info(struct drm_i915_private *i915) 
		goto mask_err;



	/* overlay on gen2 is broken and can't address above 1G */

	if (IS_GEN(i915, 2))

	if (GRAPHICS_VER(i915) == 2)

		mask_size = 30;



	/*
@@ -601,7 +601,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 
	 * device. The kernel then disables that interrupt source and so

	 * prevents the other device from working properly.

	 */

	if (INTEL_GEN(dev_priv) >= 5) {

	if (GRAPHICS_VER(dev_priv) >= 5) {

		if (pci_enable_msi(pdev) < 0)

			drm_dbg(&dev_priv->drm, "can't enable MSI");

	}
@@ -729,7 +729,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) 
			   intel_platform_name(INTEL_INFO(dev_priv)->platform),

			   intel_subplatform(RUNTIME_INFO(dev_priv),

					     INTEL_INFO(dev_priv)->platform),

			   INTEL_GEN(dev_priv));

			   GRAPHICS_VER(dev_priv));



		intel_device_info_print_static(INTEL_INFO(dev_priv), &p);

		intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
@@ -803,7 +803,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
	 */

#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)

	if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {

		if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&

		if (GRAPHICS_VER(i915) >= 9 && i915_selftest.live < 0 &&

		    i915->params.fake_lmem_start) {

			mkwrite_device_info(i915)->memory_regions =

				REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
@@ -1182,7 +1182,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 
	 * Fujitsu FSC S7110

	 * Acer Aspire 1830T

	 */

	if (!(hibernation && INTEL_GEN(dev_priv) < 6))

	if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))

		pci_set_power_state(pdev, PCI_D3hot);



out:

drivers/gpu/drm/i915/i915_gem.c

+2 −2
Original line number Diff line number Diff line
@@ -432,7 +432,7 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data, 
	/* PREAD is disallowed for all platforms after TGL-LP.  This also

	 * covers all platforms with local memory.

	 */

	if (INTEL_GEN(i915) >= 12 && !IS_TIGERLAKE(i915))

	if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))

		return -EOPNOTSUPP;



	if (args->size == 0)
@@ -712,7 +712,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 
	/* PWRITE is disallowed for all platforms after TGL-LP.  This also

	 * covers all platforms with local memory.

	 */

	if (INTEL_GEN(i915) >= 12 && !IS_TIGERLAKE(i915))

	if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))

		return -EOPNOTSUPP;



	if (args->size == 0)

drivers/gpu/drm/i915/i915_gpu_error.c

+40 −40
Original line number Diff line number Diff line
@@ -435,13 +435,13 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m, 
	err_printf(m, "  INSTDONE: 0x%08x\n",

		   ee->instdone.instdone);



	if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3)

	if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3)

		return;



	err_printf(m, "  SC_INSTDONE: 0x%08x\n",

		   ee->instdone.slice_common);



	if (INTEL_GEN(m->i915) <= 6)

	if (GRAPHICS_VER(m->i915) <= 6)

		return;



	for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
@@ -454,7 +454,7 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m, 
			   slice, subslice,

			   ee->instdone.row[slice][subslice]);



	if (INTEL_GEN(m->i915) < 12)

	if (GRAPHICS_VER(m->i915) < 12)

		return;



	err_printf(m, "  SC_INSTDONE_EXTRA: 0x%08x\n",
@@ -543,7 +543,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m, 
			   upper_32_bits(start), lower_32_bits(start),

			   upper_32_bits(end), lower_32_bits(end));

	}

	if (INTEL_GEN(m->i915) >= 4) {

	if (GRAPHICS_VER(m->i915) >= 4) {

		err_printf(m, "  BBADDR: 0x%08x_%08x\n",

			   (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);

		err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
@@ -552,14 +552,14 @@ static void error_print_engine(struct drm_i915_error_state_buf *m, 
	err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);

	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),

		   lower_32_bits(ee->faddr));

	if (INTEL_GEN(m->i915) >= 6) {

	if (GRAPHICS_VER(m->i915) >= 6) {

		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);

		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);

	}

	if (HAS_PPGTT(m->i915)) {

		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);



		if (INTEL_GEN(m->i915) >= 8) {

		if (GRAPHICS_VER(m->i915) >= 8) {

			int i;

			for (i = 0; i < 4; i++)

				err_printf(m, "  PDP%d: 0x%016llx\n",
@@ -706,25 +706,25 @@ static void err_print_gt(struct drm_i915_error_state_buf *m, 
	for (i = 0; i < gt->nfence; i++)

		err_printf(m, "  fence[%d] = %08llx\n", i, gt->fence[i]);



	if (IS_GEN_RANGE(m->i915, 6, 11)) {

	if (IS_GRAPHICS_VER(m->i915, 6, 11)) {

		err_printf(m, "ERROR: 0x%08x\n", gt->error);

		err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);

	}



	if (INTEL_GEN(m->i915) >= 8)

	if (GRAPHICS_VER(m->i915) >= 8)

		err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",

			   gt->fault_data1, gt->fault_data0);



	if (IS_GEN(m->i915, 7))

	if (GRAPHICS_VER(m->i915) == 7)

		err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);



	if (IS_GEN_RANGE(m->i915, 8, 11))

	if (IS_GRAPHICS_VER(m->i915, 8, 11))

		err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);



	if (IS_GEN(m->i915, 12))

	if (GRAPHICS_VER(m->i915) == 12)

		err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);



	if (INTEL_GEN(m->i915) >= 12) {

	if (GRAPHICS_VER(m->i915) >= 12) {

		int i;



		for (i = 0; i < GEN12_SFC_DONE_MAX; i++)
@@ -1092,12 +1092,12 @@ static void gt_record_fences(struct intel_gt_coredump *gt) 
	struct intel_uncore *uncore = gt->_gt->uncore;

	int i;



	if (INTEL_GEN(uncore->i915) >= 6) {

	if (GRAPHICS_VER(uncore->i915) >= 6) {

		for (i = 0; i < ggtt->num_fences; i++)

			gt->fence[i] =

				intel_uncore_read64(uncore,

						    FENCE_REG_GEN6_LO(i));

	} else if (INTEL_GEN(uncore->i915) >= 4) {

	} else if (GRAPHICS_VER(uncore->i915) >= 4) {

		for (i = 0; i < ggtt->num_fences; i++)

			gt->fence[i] =

				intel_uncore_read64(uncore,
@@ -1115,20 +1115,20 @@ static void engine_record_registers(struct intel_engine_coredump *ee) 
	const struct intel_engine_cs *engine = ee->engine;

	struct drm_i915_private *i915 = engine->i915;



	if (INTEL_GEN(i915) >= 6) {

	if (GRAPHICS_VER(i915) >= 6) {

		ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);



		if (INTEL_GEN(i915) >= 12)

		if (GRAPHICS_VER(i915) >= 12)

			ee->fault_reg = intel_uncore_read(engine->uncore,

							  GEN12_RING_FAULT_REG);

		else if (INTEL_GEN(i915) >= 8)

		else if (GRAPHICS_VER(i915) >= 8)

			ee->fault_reg = intel_uncore_read(engine->uncore,

							  GEN8_RING_FAULT_REG);

		else

			ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);

	}



	if (INTEL_GEN(i915) >= 4) {

	if (GRAPHICS_VER(i915) >= 4) {

		ee->esr = ENGINE_READ(engine, RING_ESR);

		ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);

		ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
@@ -1136,7 +1136,7 @@ static void engine_record_registers(struct intel_engine_coredump *ee) 
		ee->instps = ENGINE_READ(engine, RING_INSTPS);

		ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);

		ee->ccid = ENGINE_READ(engine, CCID);

		if (INTEL_GEN(i915) >= 8) {

		if (GRAPHICS_VER(i915) >= 8) {

			ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;

			ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;

		}
@@ -1155,13 +1155,13 @@ static void engine_record_registers(struct intel_engine_coredump *ee) 
	ee->head = ENGINE_READ(engine, RING_HEAD);

	ee->tail = ENGINE_READ(engine, RING_TAIL);

	ee->ctl = ENGINE_READ(engine, RING_CTL);

	if (INTEL_GEN(i915) > 2)

	if (GRAPHICS_VER(i915) > 2)

		ee->mode = ENGINE_READ(engine, RING_MI_MODE);



	if (!HWS_NEEDS_PHYSICAL(i915)) {

		i915_reg_t mmio;



		if (IS_GEN(i915, 7)) {

		if (GRAPHICS_VER(i915) == 7) {

			switch (engine->id) {

			default:

				MISSING_CASE(engine->id);
@@ -1179,7 +1179,7 @@ static void engine_record_registers(struct intel_engine_coredump *ee) 
				mmio = VEBOX_HWS_PGA_GEN7;

				break;

			}

		} else if (IS_GEN(engine->i915, 6)) {

		} else if (GRAPHICS_VER(engine->i915) == 6) {

			mmio = RING_HWS_PGA_GEN6(engine->mmio_base);

		} else {

			/* XXX: gen8 returns to sanity */
@@ -1196,13 +1196,13 @@ static void engine_record_registers(struct intel_engine_coredump *ee) 


		ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);



		if (IS_GEN(i915, 6)) {

		if (GRAPHICS_VER(i915) == 6) {

			ee->vm_info.pp_dir_base =

				ENGINE_READ(engine, RING_PP_DIR_BASE_READ);

		} else if (IS_GEN(i915, 7)) {

		} else if (GRAPHICS_VER(i915) == 7) {

			ee->vm_info.pp_dir_base =

				ENGINE_READ(engine, RING_PP_DIR_BASE);

		} else if (INTEL_GEN(i915) >= 8) {

		} else if (GRAPHICS_VER(i915) >= 8) {

			u32 base = engine->mmio_base;



			for (i = 0; i < 4; i++) {
@@ -1534,52 +1534,52 @@ static void gt_record_regs(struct intel_gt_coredump *gt) 
		gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);

	}



	if (IS_GEN(i915, 7))

	if (GRAPHICS_VER(i915) == 7)

		gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);



	if (INTEL_GEN(i915) >= 12) {

	if (GRAPHICS_VER(i915) >= 12) {

		gt->fault_data0 = intel_uncore_read(uncore,

						    GEN12_FAULT_TLB_DATA0);

		gt->fault_data1 = intel_uncore_read(uncore,

						    GEN12_FAULT_TLB_DATA1);

	} else if (INTEL_GEN(i915) >= 8) {

	} else if (GRAPHICS_VER(i915) >= 8) {

		gt->fault_data0 = intel_uncore_read(uncore,

						    GEN8_FAULT_TLB_DATA0);

		gt->fault_data1 = intel_uncore_read(uncore,

						    GEN8_FAULT_TLB_DATA1);

	}



	if (IS_GEN(i915, 6)) {

	if (GRAPHICS_VER(i915) == 6) {

		gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);

		gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);

		gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);

	}



	/* 2: Registers which belong to multiple generations */

	if (INTEL_GEN(i915) >= 7)

	if (GRAPHICS_VER(i915) >= 7)

		gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);



	if (INTEL_GEN(i915) >= 6) {

	if (GRAPHICS_VER(i915) >= 6) {

		gt->derrmr = intel_uncore_read(uncore, DERRMR);

		if (INTEL_GEN(i915) < 12) {

		if (GRAPHICS_VER(i915) < 12) {

			gt->error = intel_uncore_read(uncore, ERROR_GEN6);

			gt->done_reg = intel_uncore_read(uncore, DONE_REG);

		}

	}



	/* 3: Feature specific registers */

	if (IS_GEN_RANGE(i915, 6, 7)) {

	if (IS_GRAPHICS_VER(i915, 6, 7)) {

		gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);

		gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);

	}



	if (IS_GEN_RANGE(i915, 8, 11))

	if (IS_GRAPHICS_VER(i915, 8, 11))

		gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);



	if (IS_GEN(i915, 12))

	if (GRAPHICS_VER(i915) == 12)

		gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);



	if (INTEL_GEN(i915) >= 12) {

	if (GRAPHICS_VER(i915) >= 12) {

		for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {

			gt->sfc_done[i] =

				intel_uncore_read(uncore, GEN12_SFC_DONE(i));
@@ -1589,7 +1589,7 @@ static void gt_record_regs(struct intel_gt_coredump *gt) 
	}



	/* 4: Everything else */

	if (INTEL_GEN(i915) >= 11) {

	if (GRAPHICS_VER(i915) >= 11) {

		gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);

		gt->gtier[0] =

			intel_uncore_read(uncore,
@@ -1608,7 +1608,7 @@ static void gt_record_regs(struct intel_gt_coredump *gt) 
			intel_uncore_read(uncore,

					  GEN11_GUNIT_CSME_INTR_ENABLE);

		gt->ngtier = 6;

	} else if (INTEL_GEN(i915) >= 8) {

	} else if (GRAPHICS_VER(i915) >= 8) {

		gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);

		for (i = 0; i < 4; i++)

			gt->gtier[i] =
@@ -1618,7 +1618,7 @@ static void gt_record_regs(struct intel_gt_coredump *gt) 
		gt->ier = intel_uncore_read(uncore, DEIER);

		gt->gtier[0] = intel_uncore_read(uncore, GTIER);

		gt->ngtier = 1;

	} else if (IS_GEN(i915, 2)) {

	} else if (GRAPHICS_VER(i915) == 2) {

		gt->ier = intel_uncore_read16(uncore, GEN2_IER);

	} else if (!IS_VALLEYVIEW(i915)) {

		gt->ier = intel_uncore_read(uncore, GEN2_IER);
@@ -1674,7 +1674,7 @@ static const char *error_msg(struct i915_gpu_coredump *error) 


	len = scnprintf(error->error_msg, sizeof(error->error_msg),

			"GPU HANG: ecode %d:%x:%08x",

			INTEL_GEN(error->i915), hung_classes,

			GRAPHICS_VER(error->i915), hung_classes,

			generate_ecode(first));

	if (first && first->context.pid) {

		/* Just show the first executing process, more is confusing */