Commit 651111be authored by David Galiffi's avatar David Galiffi Committed by Alex Deucher
Browse files

drm/amd/display: Fix incorrect backlight register offset for DCN 



[Why]
Typo in backlight refactor introduced wrong register offset.

[How]
SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2).

Signed-off-by: default avatarDavid Galiffi <David.Galiffi@amd.com>
Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: <stable@vger.kernel.org>
parent d0e63b34

drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ 
	SR(BL_PWM_CNTL2), \

	SR(BL_PWM_PERIOD_CNTL), \

	SR(BL_PWM_GRP1_REG_LOCK), \

	SR(BIOS_SCRATCH_2)

	NBIO_SR(BIOS_SCRATCH_2)



#define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix