Commit 64f99159 authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code 



We got a report from Stephen/Michael that the PowerPC build was failing
with the following error:

ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses soft float
ld: failed to merge target specific data of file drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o

This error happened because of the function optc3_set_vrr_m_const. This
function expects a double as a parameter in a code that is not allowed
to have FPU operations. After further investigation, it became clear
that optc3_set_vrr_m_const was never invoked, so we can safely drop this
function and fix the ld issue.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Melissa Wen <mwen@igalia.com>
Reported-by: default avatarStephen Rothwell <sfr@canb.auug.org.au>
Reported-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Tested-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7e8a3ca9

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c

+0 −8
Original line number Diff line number Diff line
@@ -184,14 +184,6 @@ void optc3_set_dsc_config(struct timing_generator *optc, 
	REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);

}



void optc3_set_vrr_m_const(struct timing_generator *optc,

		double vtotal_avg)

{

	DC_FP_START();

	optc3_fpu_set_vrr_m_const(optc, vtotal_avg);

	DC_FP_END();

}



void optc3_set_odm_bypass(struct timing_generator *optc,

		const struct dc_crtc_timing *dc_crtc_timing)

{

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h

+0 −3
Original line number Diff line number Diff line
@@ -329,9 +329,6 @@ void optc3_lock_doublebuffer_enable(struct timing_generator *optc); 


void optc3_lock_doublebuffer_disable(struct timing_generator *optc);



void optc3_set_vrr_m_const(struct timing_generator *optc,

		double vtotal_avg);



void optc3_set_drr_trigger_window(struct timing_generator *optc,

		uint32_t window_start, uint32_t window_end);

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c

+0 −1
Original line number Diff line number Diff line
@@ -281,7 +281,6 @@ static struct timing_generator_funcs dcn32_tg_funcs = { 
		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,

		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,

		.enable_optc_clock = optc1_enable_optc_clock,

		.set_vrr_m_const = optc3_set_vrr_m_const,

		.set_drr = optc31_set_drr, // TODO: Update to optc32_set_drr once FW headers are promoted

		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,

		.set_vtotal_min_max = optc3_set_vtotal_min_max,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

+0 −2
Original line number Diff line number Diff line
@@ -302,8 +302,6 @@ struct timing_generator_funcs { 
			int group_idx,

			uint32_t gsl_ready_signal);

	void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);

	void (*set_vrr_m_const)(struct timing_generator *optc,

			double vtotal_avg);

	void (*set_drr_trigger_window)(struct timing_generator *optc,

			uint32_t window_start, uint32_t window_end);

	void (*set_vtotal_change_limit)(struct timing_generator *optc,