Loading Documentation/devicetree/bindings/net/mediatek-net.txt +5 −2 Original line number Diff line number Diff line Loading @@ -9,7 +9,8 @@ have dual GMAC each represented by a child node.. Required properties: - compatible: Should be "mediatek,mt7623-eth" - reg: Address and length of the register set for the device - interrupts: Should contain the frame engines interrupt - interrupts: Should contain the three frame engines interrupts in numeric order. These are fe_int0, fe_int1 and fe_int2. - clocks: the clock used by the core - clock-names: the names of the clock listed in the clocks property. These are "ethif", "esw", "gp2", "gp1" Loading Loading @@ -42,7 +43,9 @@ eth: ethernet@1b100000 { <ðsys CLK_ETHSYS_GP2>, <ðsys CLK_ETHSYS_GP1>; clock-names = "ethif", "esw", "gp2", "gp1"; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW GIC_SPI 199 IRQ_TYPE_LEVEL_LOW GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; resets = <ðsys MT2701_ETHSYS_ETH_RST>; reset-names = "eth"; Loading Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt +11 −7 Original line number Diff line number Diff line Loading @@ -8,15 +8,19 @@ Required properties: of memory mapped region. - clock-names: from common clock binding: Required elements: "24m" - rockchip,grf: phandle to the syscon managing the "general register files" - #phy-cells : from the generic PHY bindings, must be 0; Example: grf: syscon@ff770000 { compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; ... edp_phy: edp-phy { compatible = "rockchip,rk3288-dp-phy"; rockchip,grf = <&grf>; clocks = <&cru SCLK_EDP_24M>; clock-names = "24m"; #phy-cells = <0>; }; }; Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt +14 −8 Original line number Diff line number Diff line Loading @@ -3,17 +3,23 @@ Rockchip EMMC PHY Required properties: - compatible: rockchip,rk3399-emmc-phy - rockchip,grf : phandle to the syscon managing the "general register files" - #phy-cells: must be 0 - reg: PHY configure reg address offset in "general - reg: PHY register address offset and length in "general register files" Example: emmcphy: phy { grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; #address-cells = <1>; #size-cells = <1>; ... emmcphy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; rockchip,grf = <&grf>; reg = <0xf780>; reg = <0xf780 0x20>; #phy-cells = <0>; }; }; Documentation/devicetree/bindings/rtc/s3c-rtc.txt +4 −3 Original line number Diff line number Diff line Loading @@ -15,9 +15,10 @@ Required properties: is the rtc tick interrupt. The number of cells representing a interrupt depends on the parent interrupt controller. - clocks: Must contain a list of phandle and clock specifier for the rtc and source clocks. - clock-names: Must contain "rtc" and "rtc_src" entries sorted in the same order as the clocks property. clock and in the case of a s3c6410 compatible controller, also a source clock. - clock-names: Must contain "rtc" and for a s3c6410 compatible controller, a "rtc_src" sorted in the same order as the clocks property. Example: Loading Documentation/input/event-codes.txt +4 −0 Original line number Diff line number Diff line Loading @@ -173,6 +173,10 @@ A few EV_ABS codes have special meanings: proximity of the device and while the value of the BTN_TOUCH code is 0. If the input device may be used freely in three dimensions, consider ABS_Z instead. - BTN_TOOL_<name> should be set to 1 when the tool comes into detectable proximity and set to 0 when the tool leaves detectable proximity. BTN_TOOL_<name> signals the type of tool that is currently detected by the hardware and is otherwise independent of ABS_DISTANCE and/or BTN_TOUCH. * ABS_MT_<name>: - Used to describe multitouch input events. Please see Loading Loading
Documentation/devicetree/bindings/net/mediatek-net.txt +5 −2 Original line number Diff line number Diff line Loading @@ -9,7 +9,8 @@ have dual GMAC each represented by a child node.. Required properties: - compatible: Should be "mediatek,mt7623-eth" - reg: Address and length of the register set for the device - interrupts: Should contain the frame engines interrupt - interrupts: Should contain the three frame engines interrupts in numeric order. These are fe_int0, fe_int1 and fe_int2. - clocks: the clock used by the core - clock-names: the names of the clock listed in the clocks property. These are "ethif", "esw", "gp2", "gp1" Loading Loading @@ -42,7 +43,9 @@ eth: ethernet@1b100000 { <ðsys CLK_ETHSYS_GP2>, <ðsys CLK_ETHSYS_GP1>; clock-names = "ethif", "esw", "gp2", "gp1"; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW GIC_SPI 199 IRQ_TYPE_LEVEL_LOW GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; resets = <ðsys MT2701_ETHSYS_ETH_RST>; reset-names = "eth"; Loading
Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt +11 −7 Original line number Diff line number Diff line Loading @@ -8,15 +8,19 @@ Required properties: of memory mapped region. - clock-names: from common clock binding: Required elements: "24m" - rockchip,grf: phandle to the syscon managing the "general register files" - #phy-cells : from the generic PHY bindings, must be 0; Example: grf: syscon@ff770000 { compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; ... edp_phy: edp-phy { compatible = "rockchip,rk3288-dp-phy"; rockchip,grf = <&grf>; clocks = <&cru SCLK_EDP_24M>; clock-names = "24m"; #phy-cells = <0>; }; };
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt +14 −8 Original line number Diff line number Diff line Loading @@ -3,17 +3,23 @@ Rockchip EMMC PHY Required properties: - compatible: rockchip,rk3399-emmc-phy - rockchip,grf : phandle to the syscon managing the "general register files" - #phy-cells: must be 0 - reg: PHY configure reg address offset in "general - reg: PHY register address offset and length in "general register files" Example: emmcphy: phy { grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; #address-cells = <1>; #size-cells = <1>; ... emmcphy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; rockchip,grf = <&grf>; reg = <0xf780>; reg = <0xf780 0x20>; #phy-cells = <0>; }; };
Documentation/devicetree/bindings/rtc/s3c-rtc.txt +4 −3 Original line number Diff line number Diff line Loading @@ -15,9 +15,10 @@ Required properties: is the rtc tick interrupt. The number of cells representing a interrupt depends on the parent interrupt controller. - clocks: Must contain a list of phandle and clock specifier for the rtc and source clocks. - clock-names: Must contain "rtc" and "rtc_src" entries sorted in the same order as the clocks property. clock and in the case of a s3c6410 compatible controller, also a source clock. - clock-names: Must contain "rtc" and for a s3c6410 compatible controller, a "rtc_src" sorted in the same order as the clocks property. Example: Loading
Documentation/input/event-codes.txt +4 −0 Original line number Diff line number Diff line Loading @@ -173,6 +173,10 @@ A few EV_ABS codes have special meanings: proximity of the device and while the value of the BTN_TOUCH code is 0. If the input device may be used freely in three dimensions, consider ABS_Z instead. - BTN_TOOL_<name> should be set to 1 when the tool comes into detectable proximity and set to 0 when the tool leaves detectable proximity. BTN_TOOL_<name> signals the type of tool that is currently detected by the hardware and is otherwise independent of ABS_DISTANCE and/or BTN_TOUCH. * ABS_MT_<name>: - Used to describe multitouch input events. Please see Loading