Commit 64b2d6ff authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Greg Kroah-Hartman
Browse files

staging: mt7621-dts: align resets with binding documentation 



Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated
to be used as a reset provider. Align reset related bits and system controller
node with binding documentation along the dtsi file.

Tested-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20220110114930.1406665-5-sergio.paracuellos@gmail.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent f383b077

drivers/staging/mt7621-dts/mt7621.dtsi

+9 −12
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
#include <dt-bindings/interrupt-controller/mips-gic.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/clock/mt7621-clk.h>

#include <dt-bindings/reset/mt7621-reset.h>



/ {

	#address-cells = <1>;
@@ -67,6 +68,7 @@ 
			compatible = "mediatek,mt7621-sysc", "syscon";

			reg = <0x0 0x100>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			ralink,memctl = <&memc>;

			clock-output-names = "xtal", "cpu", "bus",

					     "50m", "125m", "150m",
@@ -96,7 +98,7 @@ 


			clocks = <&sysc MT7621_CLK_I2C>;

			clock-names = "i2c";

			resets = <&rstctrl 16>;

			resets = <&sysc MT7621_RST_I2C>;

			reset-names = "i2c";



			#address-cells = <1>;
@@ -137,7 +139,7 @@ 
			clocks = <&sysc MT7621_CLK_SPI>;

			clock-names = "spi";



			resets = <&rstctrl 18>;

			resets = <&sysc MT7621_RST_SPI>;

			reset-names = "spi";



			#address-cells = <1>;
@@ -234,11 +236,6 @@ 
		};

	};



	rstctrl: rstctrl {

		compatible = "ralink,rt2880-reset";

		#reset-cells = <1>;

	};



	sdhci: sdhci@1e130000 {

		status = "disabled";
@@ -317,7 +314,7 @@ 
		#address-cells = <1>;

		#size-cells = <0>;



		resets = <&rstctrl 6 &rstctrl 23>;

		resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>;

		reset-names = "fe", "eth";



		interrupt-parent = <&gic>;
@@ -355,7 +352,7 @@ 
				compatible = "mediatek,mt7621";

				reg = <0>;

				mediatek,mcm;

				resets = <&rstctrl 2>;

				resets = <&sysc MT7621_RST_MCM>;

				reset-names = "mcm";

				interrupt-controller;

				#interrupt-cells = <1>;
@@ -448,7 +445,7 @@ 
			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&rstctrl 24>;

			resets = <&sysc MT7621_RST_PCIE0>;

			clocks = <&sysc MT7621_CLK_PCIE0>;

			phys = <&pcie0_phy 1>;

			phy-names = "pcie-phy0";
@@ -463,7 +460,7 @@ 
			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&rstctrl 25>;

			resets = <&sysc MT7621_RST_PCIE1>;

			clocks = <&sysc MT7621_CLK_PCIE1>;

			phys = <&pcie0_phy 1>;

			phy-names = "pcie-phy1";
@@ -478,7 +475,7 @@ 
			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&rstctrl 26>;

			resets = <&sysc MT7621_RST_PCIE2>;

			clocks = <&sysc MT7621_CLK_PCIE2>;

			phys = <&pcie2_phy 0>;

			phy-names = "pcie-phy2";