Unverified Commit 64a19591 authored by Chen Lu's avatar Chen Lu Committed by Palmer Dabbelt
Browse files

riscv: fix misalgned trap vector base address 



The trap vector marked by label .Lsecondary_park must align on a
4-byte boundary, as the {m,s}tvec is defined to require 4-byte
alignment.

Signed-off-by: default avatarChen Lu <181250012@smail.nju.edu.cn>
Reviewed-by: default avatarAnup Patel <anup.patel@wdc.com>
Fixes: e011995e ("RISC-V: Move relocate and few other functions out of __init")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 3ef6ca4f

arch/riscv/kernel/head.S

+1 −0
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ setup_trap_vector: 
	csrw CSR_SCRATCH, zero

	ret



.align 2

.Lsecondary_park:

	/* We lack SMP support or have too many harts, so park this hart */

	wfi