Unverified Commit 64941199 authored Sep 30, 2024 by openeuler-ci-bot Committed by Gitee Sep 30, 2024

!11989 drm/amd/display: Fix index may exceed array range within fpu_update_bw_bounding_box

Merge Pull Request from: @ci-robot 
 
PR sync from: Huang Xiaojia <huangxiaojia2@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/SAL73C63TOJUTPVKGU5RNAFL3SARK4EV/ 
 
https://gitee.com/src-openeuler/kernel/issues/IAU9LY 
 
Link:https://gitee.com/openeuler/kernel/pulls/11989

 

Reviewed-by: Zhang Peng <zhangpeng362@huawei.com>
Signed-off-by: Zhang Peng <zhangpeng362@huawei.com>

parents ae387a2b f2bfce6c

drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -304,6 +304,16 @@ void dcn302_fpu_update_bw_bounding_box(struct dc dc, struct clk_bw_params bw_p
		dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
		}

		/* bw_params->clk_table.entries[MAX_NUM_DPM_LVL].
		* MAX_NUM_DPM_LVL is 8.
		* dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].
		* DC__VOLTAGE_STATES is 40.
		*/
		if (num_states > MAX_NUM_DPM_LVL) {
		ASSERT(0);
		return;
		}

		dcn3_02_soc.num_states = num_states;
		for (i = 0; i < dcn3_02_soc.num_states; i++) {
		dcn3_02_soc.clock_limits[i].state = i;

drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -299,6 +299,16 @@ void dcn303_fpu_update_bw_bounding_box(struct dc dc, struct clk_bw_params bw_p
		dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
		}

		/* bw_params->clk_table.entries[MAX_NUM_DPM_LVL].
		* MAX_NUM_DPM_LVL is 8.
		* dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].
		* DC__VOLTAGE_STATES is 40.
		*/
		if (num_states > MAX_NUM_DPM_LVL) {
		ASSERT(0);
		return;
		}

		dcn3_03_soc.num_states = num_states;
		for (i = 0; i < dcn3_03_soc.num_states; i++) {
		dcn3_03_soc.clock_limits[i].state = i;

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -2885,6 +2885,16 @@ void dcn32_update_bw_bounding_box_fpu(struct dc dc, struct clk_bw_params bw_pa
		dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
		}

		/* bw_params->clk_table.entries[MAX_NUM_DPM_LVL].
		* MAX_NUM_DPM_LVL is 8.
		* dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].
		* DC__VOLTAGE_STATES is 40.
		*/
		if (num_states > MAX_NUM_DPM_LVL) {
		ASSERT(0);
		return;
		}

		dcn3_2_soc.num_states = num_states;
		for (i = 0; i < dcn3_2_soc.num_states; i++) {
		dcn3_2_soc.clock_limits[i].state = i;

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -789,6 +789,16 @@ void dcn321_update_bw_bounding_box_fpu(struct dc dc, struct clk_bw_params bw_p
		dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
		}

		/* bw_params->clk_table.entries[MAX_NUM_DPM_LVL].
		* MAX_NUM_DPM_LVL is 8.
		* dcn3_02_soc.clock_limits[DC__VOLTAGE_STATES].
		* DC__VOLTAGE_STATES is 40.
		*/
		if (num_states > MAX_NUM_DPM_LVL) {
		ASSERT(0);
		return;
		}

		dcn3_21_soc.num_states = num_states;
		for (i = 0; i < dcn3_21_soc.num_states; i++) {
		dcn3_21_soc.clock_limits[i].state = i;