Commit 645afe73 authored by Eddie James's avatar Eddie James Committed by Joel Stanley
Browse files

ARM: dts: aspeed: ast2600: Update XDMA engine node 



Add the PCI-E root complex reset, correct the pcie-device property, and
add the Aspeed SCU interrupt controller include.

Signed-off-by: default avatarEddie James <eajames@linux.ibm.com>
Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
parent b3e10b5e

arch/arm/boot/dts/aspeed-g6.dtsi

+3 −12
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
// Copyright 2019 IBM Corp.



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>

#include <dt-bindings/clock/ast2600-clock.h>



/ {
@@ -346,22 +347,12 @@ 
				resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>;

				reset-names = "device", "root-complex";

				interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

						      <&scu_ic0 2>;

				pcie-device = "bmc";

						      <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>;

				aspeed,pcie-device = "bmc";

				aspeed,scu = <&syscon>;

				status = "disabled";

			};



			video: video@1e700000 {

				compatible = "aspeed,ast2600-video-engine";

				reg = <0x1e700000 0x1000>;

				clocks = <&syscon ASPEED_CLK_GATE_VCLK>,

					 <&syscon ASPEED_CLK_GATE_ECLK>;

				clock-names = "vclk", "eclk";

				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

			};



			gpio0: gpio@1e780000 {

				#gpio-cells = <2>;

				gpio-controller;