Commit 6449dcb0 authored by Kirill A. Shutemov's avatar Kirill A. Shutemov Committed by Dave Hansen
Browse files

x86: CPUID and CR3/CR4 flags for Linear Address Masking 



Enumerate Linear Address Masking and provide defines for CR3 and CR4
flags.

The new CONFIG_ADDRESS_MASKING option enables the feature support in
kernel.

Signed-off-by: default avatarKirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: default avatarAlexander Potapenko <glider@google.com>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: default avatarAlexander Potapenko <glider@google.com>
Link: https://lore.kernel.org/all/20230312112612.31869-4-kirill.shutemov%40linux.intel.com
parent 5ef495e5

arch/x86/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -2290,6 +2290,17 @@ config RANDOMIZE_MEMORY_PHYSICAL_PADDING 


	  If unsure, leave at the default value.



config ADDRESS_MASKING

	bool "Linear Address Masking support"

	depends on X86_64

	help

	  Linear Address Masking (LAM) modifies the checking that is applied

	  to 64-bit linear addresses, allowing software to use of the

	  untranslated address bits for metadata.



	  The capability can be used for efficient address sanitizers (ASAN)

	  implementation and for optimizations in JITs.



config HOTPLUG_CPU

	def_bool y

	depends on SMP

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -321,6 +321,7 @@ 
#define X86_FEATURE_LKGS		(12*32+18) /* "" Load "kernel" (userspace) GS */

#define X86_FEATURE_AMX_FP16		(12*32+21) /* "" AMX fp16 Support */

#define X86_FEATURE_AVX_IFMA            (12*32+23) /* "" Support for VPMADD52[H,L]UQ */

#define X86_FEATURE_LAM			(12*32+26) /* Linear Address Masking */



/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

arch/x86/include/asm/processor-flags.h

+2 −0
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ 
 * On systems with SME, one bit (in a variable position!) is stolen to indicate

 * that the top-level paging structure is encrypted.

 *

 * On systemms with LAM, bits 61 and 62 are used to indicate LAM mode.

 *

 * All of the remaining bits indicate the physical address of the top-level

 * paging structure.

 *

arch/x86/include/uapi/asm/processor-flags.h

+6 −0
Original line number Diff line number Diff line
@@ -82,6 +82,10 @@ 
#define X86_CR3_PCID_BITS	12

#define X86_CR3_PCID_MASK	(_AC((1UL << X86_CR3_PCID_BITS) - 1, UL))



#define X86_CR3_LAM_U57_BIT	61 /* Activate LAM for userspace, 62:57 bits masked */

#define X86_CR3_LAM_U57		_BITULL(X86_CR3_LAM_U57_BIT)

#define X86_CR3_LAM_U48_BIT	62 /* Activate LAM for userspace, 62:48 bits masked */

#define X86_CR3_LAM_U48		_BITULL(X86_CR3_LAM_U48_BIT)

#define X86_CR3_PCID_NOFLUSH_BIT 63 /* Preserve old PCID */

#define X86_CR3_PCID_NOFLUSH    _BITULL(X86_CR3_PCID_NOFLUSH_BIT)
@@ -132,6 +136,8 @@ 
#define X86_CR4_PKE		_BITUL(X86_CR4_PKE_BIT)

#define X86_CR4_CET_BIT		23 /* enable Control-flow Enforcement Technology */

#define X86_CR4_CET		_BITUL(X86_CR4_CET_BIT)

#define X86_CR4_LAM_SUP_BIT	28 /* LAM for supervisor pointers */

#define X86_CR4_LAM_SUP		_BITUL(X86_CR4_LAM_SUP_BIT)



/*

 * x86-64 Task Priority Register, CR8