Commit 643feb00 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Joerg Roedel
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iommu/amd: Add support for Guest IO protection 



AMD IOMMU introduces support for Guest I/O protection where the request
from the I/O device without a PASID are treated as if they have PASID 0.

Co-developed-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Signed-off-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Link: https://lore.kernel.org/r/20220825063939.8360-8-vasant.hegde@amd.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent aaac38f6

drivers/iommu/amd/amd_iommu_types.h

+3 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ 
#define FEATURE_HE		(1ULL<<8)

#define FEATURE_PC		(1ULL<<9)

#define FEATURE_GAM_VAPIC	(1ULL<<21)

#define FEATURE_GIOSUP		(1ULL<<48)

#define FEATURE_EPHSUP		(1ULL<<50)

#define FEATURE_SNP		(1ULL<<63)
@@ -378,6 +379,7 @@ 
#define DTE_FLAG_IW (1ULL << 62)



#define DTE_FLAG_IOTLB	(1ULL << 32)

#define DTE_FLAG_GIOV	(1ULL << 54)

#define DTE_FLAG_GV	(1ULL << 55)

#define DTE_FLAG_MASK	(0x3ffULL << 32)

#define DTE_GLX_SHIFT	(56)
@@ -436,6 +438,7 @@ 
#define PD_PASSTHROUGH_MASK	(1UL << 2) /* domain has no page

					      translation */

#define PD_IOMMUV2_MASK		(1UL << 3) /* domain has gcr3 table */

#define PD_GIOV_MASK		(1UL << 4) /* domain enable GIOV support */



extern bool amd_iommu_dump;

#define DUMP_printk(format, arg...)				\

drivers/iommu/amd/init.c

+13 −0
Original line number Diff line number Diff line
@@ -2068,6 +2068,17 @@ static int __init iommu_init_pci(struct amd_iommu *iommu) 


	init_iommu_perf_ctr(iommu);



	if (amd_iommu_pgtable == AMD_IOMMU_V2) {

		if (!iommu_feature(iommu, FEATURE_GIOSUP) ||

		    !iommu_feature(iommu, FEATURE_GT)) {

			pr_warn("Cannot enable v2 page table for DMA-API. Fallback to v1.\n");

			amd_iommu_pgtable = AMD_IOMMU_V1;

		} else if (iommu_default_passthrough()) {

			pr_warn("V2 page table doesn't support passthrough mode. Fallback to v1.\n");

			amd_iommu_pgtable = AMD_IOMMU_V1;

		}

	}



	if (is_rd890_iommu(iommu->dev)) {

		int i, j;
@@ -2146,6 +2157,8 @@ static void print_iommu_info(void) 
		if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)

			pr_info("X2APIC enabled\n");

	}

	if (amd_iommu_pgtable == AMD_IOMMU_V2)

		pr_info("V2 page table enabled\n");

}



static int __init amd_iommu_init_pci(void)

drivers/iommu/amd/iommu.c

+3 −0
Original line number Diff line number Diff line
@@ -1597,6 +1597,9 @@ static void set_dte_entry(struct amd_iommu *iommu, u16 devid, 


		tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;

		flags    |= tmp;



		if (domain->flags & PD_GIOV_MASK)

			pte_root |= DTE_FLAG_GIOV;

	}



	flags &= ~DEV_DOMID_MASK;