Commit 6423035f authored by Ben Widawsky's avatar Ben Widawsky Committed by Dan Williams
Browse files

cxl/hdm: Fix decoder count calculation 



The decoder count in the HDM decoder capability structure is an encoded
field. As defined in the spec:

Decoder Count: Reports the number of memory address decoders implemented
by the component.
0 – 1 Decoder
1 – 2 Decoders
2 – 4 Decoders
3 – 6 Decoders
4 – 8 Decoders
5 – 10 Decoders
All other values are reserved

Nothing is actually fixed by this as nothing actually used this mapping
yet.

Cc: Ira Weiny <ira.weiny@intel.com>
Fixes: 08422378 ("cxl/pci: Add HDM decoder capabilities")
Acked-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarBen Widawsky <ben.widawsky@intel.com>
Link: https://lore.kernel.org/r/20210611190111.121295-1-ben.widawsky@intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 40ba17af

drivers/cxl/core.c

+1 −1
Original line number Diff line number Diff line
@@ -595,7 +595,7 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, 


			hdr = readl(register_block);



			decoder_cnt = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, hdr);

			decoder_cnt = cxl_hdm_decoder_count(hdr);

			length = 0x20 * decoder_cnt + 0x10;



			map->hdm_decoder.valid = true;

drivers/cxl/cxl.h

+7 −0
Original line number Diff line number Diff line
@@ -41,6 +41,13 @@ 
#define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET 0x1c

#define CXL_HDM_DECODER0_CTRL_OFFSET 0x20



static inline int cxl_hdm_decoder_count(u32 cap_hdr)

{

	int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);



	return val ? val * 2 : 1;

}



/* CXL 2.0 8.2.8.1 Device Capabilities Array Register */

#define CXLDEV_CAP_ARRAY_OFFSET 0x0

#define   CXLDEV_CAP_ARRAY_CAP_ID 0