Commit 640c8d87 authored Oct 27, 2022 by Muchun Song Committed by Zheng Zengkai Oct 27, 2022

arm64: avoid flushing icache multiple times on contiguous HugeTLB

mainline inclusion
from mainline-v5.18-rc1
commit cf5a501d
category: bugfix
bugzilla: 187198, https://gitee.com/openeuler/kernel/issues/I5Q9PS
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cf5a501d985ba1b6ace9b18c64346441819bffea



--------------------------------

When a contiguous HugeTLB page is mapped, set_pte_at() will be called
CONT_PTES/CONT_PMDS times.  Therefore, __sync_icache_dcache() will
flush cache multiple times if the page is executable (to ensure
the I-D cache coherency).  However, the first flushing cache already
covers subsequent cache flush operations.  So only flusing cache
for the head page if it is a HugeTLB page to avoid redundant cache
flushing.  In the next patch, it is also depends on this change
since the tail vmemmap pages of HugeTLB is mapped with read-only
meanning only head page struct can be modified.

Signed-off-by: Muchun Song <songmuchun@bytedance.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220302084624.33340-1-songmuchun@bytedance.com


Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>

parent 0073794f

arch/arm64/mm/flush.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -55,6 +55,13 @@ void __sync_icache_dcache(pte_t pte)
		{
		struct page *page = pte_page(pte);

		/*
		* HugeTLB pages are always fully mapped, so only setting head page's
		* PG_dcache_clean flag is enough.
		*/
		if (PageHuge(page))
		page = compound_head(page);

		if (!test_bit(PG_dcache_clean, &page->flags)) {
		sync_icache_aliases(page_address(page), page_size(page));
		set_bit(PG_dcache_clean, &page->flags);