Commit 63fbe9db authored by David Jander's avatar David Jander Committed by Marek Vasut
Browse files

drm/bridge: tc358767: increase PLL lock time delay 



The PLL often fails to lock with this delay. The new value was
determined by trial and error increasing the delay bit by bit
until the error did not occurr anymore even after several tries.
Then double that value was taken as the minimum delay to be safe.

Signed-off-by: default avatarDavid Jander <david@protonic.nl>
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Reviewed-by: default avatarMarek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de> # TC9595
Reviewed-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20230721165328.3968759-1-l.stach@pengutronix.de
parent 4cfe5cc0

drivers/gpu/drm/bridge/tc358767.c

+2 −2
Original line number Diff line number Diff line
@@ -500,8 +500,8 @@ static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) 
	if (ret)

		return ret;



	/* Wait for PLL to lock: up to 2.09 ms, depending on refclk */

	usleep_range(3000, 6000);

	/* Wait for PLL to lock: up to 7.5 ms, depending on refclk */

	usleep_range(15000, 20000);



	return 0;

}