Commit 63ef1a8a authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-fixes-5.18-1' of...

Merge tag 'irqchip-fixes-5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip fixes from Marc Zyngier:

 - Fix GICv3 polling for RWP in redistributors

 - Reject ACPI attempts to use SGIs on GIC/GICv3

 - Fix unpredictible behaviour when making a VPE non-resident
   with GICv4

 - A couple of fixes for the newly merged qcom-mpm driver

Link: https://lore.kernel.org/lkml/20220409094229.267649-1-maz@kernel.org
parents 31231092 544808f7
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+1 −0
Original line number Diff line number Diff line
@@ -433,6 +433,7 @@ config QCOM_PDC
config QCOM_MPM
	tristate "QCOM MPM"
	depends on ARCH_QCOM
	depends on MAILBOX
	select IRQ_DOMAIN_HIERARCHY
	help
	  MSM Power Manager driver to manage and configure wakeup
+19 −9
Original line number Diff line number Diff line
@@ -3011,18 +3011,12 @@ static int __init allocate_lpi_tables(void)
	return 0;
}

static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
static u64 read_vpend_dirty_clear(void __iomem *vlpi_base)
{
	u32 count = 1000000;	/* 1s! */
	bool clean;
	u64 val;

	val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
	val &= ~GICR_VPENDBASER_Valid;
	val &= ~clr;
	val |= set;
	gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);

	do {
		val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
		clean = !(val & GICR_VPENDBASER_Dirty);
@@ -3033,11 +3027,27 @@ static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
		}
	} while (!clean && count);

	if (unlikely(val & GICR_VPENDBASER_Dirty)) {
	if (unlikely(!clean))
		pr_err_ratelimited("ITS virtual pending table not cleaning\n");
		val |= GICR_VPENDBASER_PendingLast;

	return val;
}

static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
{
	u64 val;

	/* Make sure we wait until the RD is done with the initial scan */
	val = read_vpend_dirty_clear(vlpi_base);
	val &= ~GICR_VPENDBASER_Valid;
	val &= ~clr;
	val |= set;
	gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);

	val = read_vpend_dirty_clear(vlpi_base);
	if (unlikely(val & GICR_VPENDBASER_Dirty))
		val |= GICR_VPENDBASER_PendingLast;

	return val;
}

+10 −4
Original line number Diff line number Diff line
@@ -206,11 +206,11 @@ static inline void __iomem *gic_dist_base(struct irq_data *d)
	}
}

static void gic_do_wait_for_rwp(void __iomem *base)
static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
{
	u32 count = 1000000;	/* 1s! */

	while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
	while (readl_relaxed(base + GICD_CTLR) & bit) {
		count--;
		if (!count) {
			pr_err_ratelimited("RWP timeout, gone fishing\n");
@@ -224,13 +224,13 @@ static void gic_do_wait_for_rwp(void __iomem *base)
/* Wait for completion of a distributor change */
static void gic_dist_wait_for_rwp(void)
{
	gic_do_wait_for_rwp(gic_data.dist_base);
	gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
}

/* Wait for completion of a redistributor change */
static void gic_redist_wait_for_rwp(void)
{
	gic_do_wait_for_rwp(gic_data_rdist_rd_base());
	gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
}

#ifdef CONFIG_ARM64
@@ -1466,6 +1466,12 @@ static int gic_irq_domain_translate(struct irq_domain *d,
		if(fwspec->param_count != 2)
			return -EINVAL;

		if (fwspec->param[0] < 16) {
			pr_err(FW_BUG "Illegal GSI%d translation request\n",
			       fwspec->param[0]);
			return -EINVAL;
		}

		*hwirq = fwspec->param[0];
		*type = fwspec->param[1];

+6 −0
Original line number Diff line number Diff line
@@ -1123,6 +1123,12 @@ static int gic_irq_domain_translate(struct irq_domain *d,
		if(fwspec->param_count != 2)
			return -EINVAL;

		if (fwspec->param[0] < 16) {
			pr_err(FW_BUG "Illegal GSI%d translation request\n",
			       fwspec->param[0]);
			return -EINVAL;
		}

		*hwirq = fwspec->param[0];
		*type = fwspec->param[1];

+1 −1
Original line number Diff line number Diff line
@@ -375,7 +375,7 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent)
	raw_spin_lock_init(&priv->lock);

	priv->base = devm_platform_ioremap_resource(pdev, 0);
	if (!priv->base)
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	for (i = 0; i < priv->reg_stride; i++) {