Commit 63e96bc4 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-phy-cleanups' 



Weihang Li says:

====================
net: phy: fix some coding-style issues

Make some cleanups according to the coding style of kernel.

Changes since v1:
- Update commit description of #1 and #3.
- Avoid changing the indentation in #2.
- Change a group of if-else statement into switch from #4 and put it into
  a single patch.
- Put '|' at the end of line in #5 and #7.
- Avoid deleting spaces in definition of 'settings' in #5.
- Drop #8 from the series which needs more discussion with David.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 56a967c4 16d4d650

drivers/net/phy/bcm87xx.c

+2 −2
Original line number Diff line number Diff line
@@ -54,9 +54,9 @@ static int bcm87xx_of_reg_init(struct phy_device *phydev) 
		u16 reg		= be32_to_cpup(paddr++);

		u16 mask	= be32_to_cpup(paddr++);

		u16 val_bits	= be32_to_cpup(paddr++);

		int val;

		u32 regnum = mdiobus_c45_addr(devid, reg);

		val = 0;

		int val = 0;



		if (mask) {

			val = phy_read(phydev, regnum);

			if (val < 0) {

drivers/net/phy/davicom.c

+3 −3
Original line number Diff line number Diff line
@@ -45,8 +45,8 @@ 
#define MII_DM9161_INTR_LINK_CHANGE	0x0004

#define MII_DM9161_INTR_INIT		0x0000

#define MII_DM9161_INTR_STOP	\

(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \

 | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)

	(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK |	\

	 MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)

#define MII_DM9161_INTR_CHANGE	\

	(MII_DM9161_INTR_DPLX_CHANGE | \

	 MII_DM9161_INTR_SPD_CHANGE | \

drivers/net/phy/dp83640.c

+3 −2
Original line number Diff line number Diff line
@@ -170,9 +170,9 @@ static ushort gpio_tab[GPIO_TABLE_SIZE] = { 
module_param(chosen_phy, int, 0444);

module_param_array(gpio_tab, ushort, NULL, 0444);



MODULE_PARM_DESC(chosen_phy, \

MODULE_PARM_DESC(chosen_phy,

	"The address of the PHY to use for the ancillary clock features");

MODULE_PARM_DESC(gpio_tab, \

MODULE_PARM_DESC(gpio_tab,

	"Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");



static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
@@ -615,6 +615,7 @@ static void prune_rx_ts(struct dp83640_private *dp83640) 
static void enable_broadcast(struct phy_device *phydev, int init_page, int on)

{

	int val;



	phy_write(phydev, PAGESEL, 0);

	val = phy_read(phydev, PHYCR2);

	if (on)

drivers/net/phy/et1011c.c

+8 −7
Original line number Diff line number Diff line
@@ -46,8 +46,8 @@ MODULE_LICENSE("GPL"); 


static int et1011c_config_aneg(struct phy_device *phydev)

{

	int ctl = 0;

	ctl = phy_read(phydev, MII_BMCR);

	int ctl = phy_read(phydev, MII_BMCR);



	if (ctl < 0)

		return ctl;

	ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
@@ -60,9 +60,10 @@ static int et1011c_config_aneg(struct phy_device *phydev) 


static int et1011c_read_status(struct phy_device *phydev)

{

	static int speed;

	int ret;

	u32 val;

	static int speed;



	ret = genphy_read_status(phydev);



	if (speed != phydev->speed) {
@@ -72,10 +73,10 @@ static int et1011c_read_status(struct phy_device *phydev) 
					ET1011C_GIGABIT_SPEED) {

			val = phy_read(phydev, ET1011C_CONFIG_REG);

			val &= ~ET1011C_TX_FIFO_MASK;

			phy_write(phydev, ET1011C_CONFIG_REG, val\

					| ET1011C_GMII_INTERFACE\

					| ET1011C_SYS_CLK_EN\

					| ET1011C_TX_FIFO_DEPTH_16);

			phy_write(phydev, ET1011C_CONFIG_REG, val |

					  ET1011C_GMII_INTERFACE |

					  ET1011C_SYS_CLK_EN |

					  ET1011C_TX_FIFO_DEPTH_16);



		}

	}

drivers/net/phy/fixed_phy.c

+2 −2
Original line number Diff line number Diff line
@@ -161,8 +161,8 @@ static int fixed_phy_add_gpiod(unsigned int irq, int phy_addr, 
}



int fixed_phy_add(unsigned int irq, int phy_addr,

		  struct fixed_phy_status *status) {



		  struct fixed_phy_status *status)

{

	return fixed_phy_add_gpiod(irq, phy_addr, status, NULL);

}

EXPORT_SYMBOL_GPL(fixed_phy_add);