Commit 63caca1e authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'fec-next' 



Joakim Zhang says:

====================
net: fec: add support for i.MX8MQ and i.MX8QM

This patch set adds supports for i.MX8MQ and i.MX8QM, both of them extend new features.

ChangeLogs:
V1->V2:
	* rebase on schema binding, and update dts compatible string.
	* use generic ethernet controller property for MAC internal RGMII clock delay
	  rx-internal-delay-ps and tx-internal-delay-ps
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 68f98848 987e1b96

Documentation/devicetree/bindings/net/fsl,fec.yaml

+27 −0
Original line number Diff line number Diff line
@@ -40,6 +40,24 @@ properties: 
          - enum:

              - fsl,imx7d-fec

          - const: fsl,imx6sx-fec

      - items:

          - const: fsl,imx8mq-fec

          - const: fsl,imx6sx-fec

      - items:

          - enum:

              - fsl,imx8mm-fec

              - fsl,imx8mn-fec

              - fsl,imx8mp-fec

          - const: fsl,imx8mq-fec

          - const: fsl,imx6sx-fec

      - items:

          - const: fsl,imx8qm-fec

          - const: fsl,imx6sx-fec

      - items:

          - enum:

              - fsl,imx8qxp-fec

          - const: fsl,imx8qm-fec

          - const: fsl,imx6sx-fec



  reg:

    maxItems: 1
@@ -78,6 +96,8 @@ properties: 
      SOC internal PLL.

      The "enet_out"(option), output clock for external device, like supply clock

      for PHY. The clock is required if PHY clock source from SOC.

      The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.

      The clock is required if SoC RGMII enable clock delay.



  clock-names:

    minItems: 2
@@ -89,6 +109,7 @@ properties: 
        - ptp

        - enet_clk_ref

        - enet_out

        - enet_2x_txclk



  phy-mode: true
@@ -100,6 +121,12 @@ properties: 


  mac-address: true



  tx-internal-delay-ps:

    enum: [0, 2000]



  rx-internal-delay-ps:

    enum: [0, 2000]



  phy-supply:

    description:

      Regulator that powers the Ethernet PHY.

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -920,7 +920,7 @@ 
			};



			fec1: ethernet@30be0000 {

				compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";

				compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";

				reg = <0x30be0000 0x10000>;

				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

arch/arm64/boot/dts/freescale/imx8mn.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -923,7 +923,7 @@ 
			};



			fec1: ethernet@30be0000 {

				compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";

				compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";

				reg = <0x30be0000 0x10000>;

				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -17,9 +17,9 @@ 
};



&fec1 {

	compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";

	compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";

};



&fec2 {

	compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";

	compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";

};

drivers/net/ethernet/freescale/fec.h

+25 −0
Original line number Diff line number Diff line
@@ -77,6 +77,8 @@ 
#define FEC_R_DES_ACTIVE_2	0x1e8 /* Rx descriptor active for ring 2 */

#define FEC_X_DES_ACTIVE_2	0x1ec /* Tx descriptor active for ring 2 */

#define FEC_QOS_SCHEME		0x1f0 /* Set multi queues Qos scheme */

#define FEC_LPI_SLEEP		0x1f4 /* Set IEEE802.3az LPI Sleep Ts time */

#define FEC_LPI_WAKE		0x1f8 /* Set IEEE802.3az LPI Wake Tw time */

#define FEC_MIIGSK_CFGR		0x300 /* MIIGSK Configuration reg */

#define FEC_MIIGSK_ENR		0x308 /* MIIGSK Enable reg */
@@ -379,6 +381,9 @@ struct bufdesc_ex { 
#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF)

#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))



#define FEC_ENET_TXC_DLY	((uint)0x00010000)

#define FEC_ENET_RXC_DLY	((uint)0x00020000)



/* ENET interrupt coalescing macro define */

#define FEC_ITR_CLK_SEL		(0x1 << 30)

#define FEC_ITR_EN		(0x1 << 31)
@@ -472,6 +477,19 @@ struct bufdesc_ex { 
 */

#define FEC_QUIRK_HAS_MULTI_QUEUES	(1 << 19)



/* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE

 * standard. For the transmission, MAC supply two user registers to set

 * Sleep (TS) and Wake (TW) time.

 */

#define FEC_QUIRK_HAS_EEE		(1 << 20)



/* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC

 * as an alternative option to make sure it works well with various PHYs.

 * For the implementation of delayed clock, ENET takes synchronized 250MHz

 * clocks to generate 2ns delay.

 */

#define FEC_QUIRK_DELAYED_CLKS_SUPPORT	(1 << 21)



struct bufdesc_prop {

	int qid;

	/* Address of Rx and Tx buffers */
@@ -528,6 +546,7 @@ struct fec_enet_private { 
	struct clk *clk_ref;

	struct clk *clk_enet_out;

	struct clk *clk_ptp;

	struct clk *clk_2x_txclk;



	bool ptp_clk_on;

	struct mutex ptp_clk_mutex;
@@ -550,6 +569,8 @@ struct fec_enet_private { 
	uint	phy_speed;

	phy_interface_t	phy_interface;

	struct device_node *phy_node;

	bool	rgmii_txc_dly;

	bool	rgmii_rxc_dly;

	int	link;

	int	full_duplex;

	int	speed;
@@ -589,6 +610,10 @@ struct fec_enet_private { 
	unsigned int tx_time_itr;

	unsigned int itr_clk_rate;



	/* tx lpi eee mode */

	struct ethtool_eee eee;

	unsigned int clk_ref_rate;



	u32 rx_copybreak;



	/* ptp clock period in ns*/