Unverified Commit 63ba67eb authored by Atish Patra's avatar Atish Patra Committed by Palmer Dabbelt
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RISC-V: Move counter info definition to sbi header file 



Counter info encoding format is defined by the SBI specificaiton.
KVM implementation of SBI PMU extension will also leverage this definition.
Move the definition to common sbi header file from the sbi pmu driver.

Signed-off-by: default avatarAtish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20220711174632.4186047-5-atishp@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 0209b583

arch/riscv/include/asm/sbi.h

+14 −0
Original line number Diff line number Diff line
@@ -122,6 +122,20 @@ enum sbi_ext_pmu_fid { 
	SBI_EXT_PMU_COUNTER_FW_READ,

};



union sbi_pmu_ctr_info {

	unsigned long value;

	struct {

		unsigned long csr:12;

		unsigned long width:6;

#if __riscv_xlen == 32

		unsigned long reserved:13;

#else

		unsigned long reserved:45;

#endif

		unsigned long type:1;

	};

};



#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(55, 0)

#define RISCV_PMU_RAW_EVENT_IDX 0x20000

drivers/perf/riscv_pmu_sbi.c

+0 −14
Original line number Diff line number Diff line
@@ -21,20 +21,6 @@ 
#include <asm/sbi.h>

#include <asm/hwcap.h>



union sbi_pmu_ctr_info {

	unsigned long value;

	struct {

		unsigned long csr:12;

		unsigned long width:6;

#if __riscv_xlen == 32

		unsigned long reserved:13;

#else

		unsigned long reserved:45;

#endif

		unsigned long type:1;

	};

};



/*

 * RISC-V doesn't have hetergenous harts yet. This need to be part of

 * per_cpu in case of harts with different pmu counters