Commit 638971b7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC updates from Ulf Hansson:
 "MMC core:

   - Support zero-out using TRIM for eMMC

   - Allow to override the busy-timeout for the ioctl-cmds

  MMC host:

   - Continued the conversion of DT bindings into the JSON schema

   - jz4740: Apply DMA engine limits to maximum segment size

   - mmci_stm32: Use a buffer for unaligned DMA requests

   - mmc_spi: Enabled high-speed modes via parsing of DT

   - omap: Make clock management to be compliant with CCF

   - renesas_sdhi:
      - Support eMMC HS400 mode for R-Car V3H ES2.0
      - Don't allow support for eMMC HS400 for R-Car V3M/D3

   - sdhci_am654: Fix problem when SD card slot lacks the card detect
     line

   - sdhci-esdhc-imx: Add support for the imx8dxl variant

   - sdhci-brcmstb: Enable support for clock gating to save power

   - sdhci-msm:
      - Add support for the sdx65 variant
      - Add support for the sm8150 variant

   - sdhci-of-dwcmshc: Add support for the Rockchip rk3588 variant

   - sdhci-pci-gli: Add workaround to allow GL9755 to enter ASPM L1.2"

* tag 'mmc-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (52 commits)
  mmc: sdhci-of-arasan: Add NULL check for data field
  mmc: core: Support zeroout using TRIM for eMMC
  mmc: sdhci-brcmstb: Fix compiler warning
  mmc: sdhci-msm: Add compatible string check for sdx65
  dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible
  mmc: sdhci-msm: Add compatible string check for sm8150
  dt-bindings: mmc: sdhci-msm: Add compatible string for sm8150
  mmc: sdhci-msm: Add SoC specific compatibles
  dt-bindings: mmc: sdhci-msm: Convert bindings to yaml
  dt-bindings: mmc: brcm,sdhci-brcmstb: cleanup example
  dt-bindings: mmc: brcm,sdhci-brcmstb: correct number of reg entries
  mmc: sdhci-brcmstb: Enable Clock Gating to save power
  mmc: sdhci-brcmstb: Re-organize flags
  mmc: mmci: Remove custom ios handler
  mmc: atmel-mci: Simplify if(chan) and if(!chan)
  mmc: core: use kobj_to_dev()
  dt-bindings: mmc: sdhci-of-dwcmhsc: Add rk3588
  mmc: core: Add CIDs for cards to the entropy pool
  mmc: core: Allows to override the timeout value for ioctl() path
  mmc: sdhci-omap: Use of_device_get_match_data() helper
  ...
parents b1b5bf16 ded2c4c3

Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml

+10 −10
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ properties: 
          - const: brcm,sdhci-brcmstb



  reg:

    minItems: 2

    maxItems: 2



  reg-names:

    items:
@@ -65,15 +65,15 @@ unevaluatedProperties: false 
examples:

  - |

    mmc@84b0000 {

      sd-uhs-sdr50;

      sd-uhs-ddr50;

      sd-uhs-sdr104;

      sdhci,auto-cmd12;

      compatible = "brcm,bcm7216-sdhci",

                   "brcm,bcm7445-sdhci",

                   "brcm,sdhci-brcmstb";

      reg = <0x84b0000 0x260>, <0x84b0300 0x200>;

      reg-names = "host", "cfg";

      sd-uhs-sdr50;

      sd-uhs-ddr50;

      sd-uhs-sdr104;

      sdhci,auto-cmd12;

      interrupts = <0x0 0x26 0x4>;

      interrupt-names = "sdio0_0";

      clocks = <&scmi_clk 245>;
@@ -81,6 +81,11 @@ examples: 
    };



    mmc@84b1000 {

      compatible = "brcm,bcm7216-sdhci",

                   "brcm,bcm7445-sdhci",

                   "brcm,sdhci-brcmstb";

      reg = <0x84b1000 0x260>, <0x84b1300 0x200>;

      reg-names = "host", "cfg";

      mmc-ddr-1_8v;

      mmc-hs200-1_8v;

      mmc-hs400-1_8v;
@@ -88,11 +93,6 @@ examples: 
      supports-cqe;

      non-removable;

      bus-width = <0x8>;

      compatible = "brcm,bcm7216-sdhci",

           "brcm,bcm7445-sdhci",

            "brcm,sdhci-brcmstb";

      reg = <0x84b1000 0x260>, <0x84b1300 0x200>;

      reg-names = "host", "cfg";

      interrupts = <0x0 0x27 0x4>;

      interrupt-names = "sdio1_0";

      clocks = <&scmi_clk 245>;

Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml

+28 −3
Original line number Diff line number Diff line
@@ -34,22 +34,47 @@ properties: 
          - fsl,imx6ull-usdhc

          - fsl,imx7d-usdhc

          - fsl,imx7ulp-usdhc

          - fsl,imx8mm-usdhc

          - fsl,imxrt1050-usdhc

          - nxp,s32g2-usdhc

      - items:

          - enum:

              - fsl,imx8mq-usdhc

          - const: fsl,imx7d-usdhc

      - items:

          - enum:

              - fsl,imx8mn-usdhc

              - fsl,imx8mp-usdhc

              - fsl,imx93-usdhc

              - fsl,imx8ulp-usdhc

          - const: fsl,imx8mm-usdhc

      - items:

          - enum:

              - fsl,imx8qm-usdhc

          - const: fsl,imx8qxp-usdhc

      - items:

          - enum:

              - fsl,imx8dxl-usdhc

              - fsl,imx8mm-usdhc

              - fsl,imx8mn-usdhc

              - fsl,imx8mp-usdhc

              - fsl,imx8mq-usdhc

              - fsl,imx8qm-usdhc

              - fsl,imx8qxp-usdhc

          - const: fsl,imx7d-usdhc

        deprecated: true

      - items:

          - enum:

              - fsl,imx93-usdhc

              - fsl,imx8ulp-usdhc

              - fsl,imx8mn-usdhc

              - fsl,imx8mp-usdhc

          - const: fsl,imx8mm-usdhc

          - const: fsl,imx7d-usdhc

        deprecated: true

      - items:

          - enum:

              - fsl,imx8qm-usdhc

          - const: fsl,imx8qxp-usdhc

          - const: fsl,imx7d-usdhc

        deprecated: true



  reg:

    maxItems: 1

Documentation/devicetree/bindings/mmc/marvell,dove-sdhci.yaml

0 → 100644
+44 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mmc/marvell,dove-sdhci.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Marvell sdhci-dove controller



maintainers:

  - Adrian Hunter <adrian.hunter@intel.com>

  - Ulf Hansson <ulf.hansson@linaro.org>



allOf:

  - $ref: mmc-controller.yaml#



properties:

  compatible:

    const: marvell,dove-sdhci



  reg:

    maxItems: 1



  interrupts:

    minItems: 1

    maxItems: 2



  clocks:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts



unevaluatedProperties: false



examples:

  - |

    sdio0: mmc@92000 {

      compatible = "marvell,dove-sdhci";

      reg = <0x92000 0x100>;

      interrupts = <35>;

      clocks = <&gate_clk 9>;

    };

Documentation/devicetree/bindings/mmc/marvell,orion-sdio.yaml

0 → 100644
+44 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mmc/marvell,orion-sdio.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Marvell orion-sdio controller



maintainers:

  - Nicolas Pitre <nico@fluxnic.net>

  - Ulf Hansson <ulf.hansson@linaro.org>



allOf:

  - $ref: mmc-controller.yaml#



properties:

  compatible:

    const: marvell,orion-sdio



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts

  - clocks



unevaluatedProperties: false



examples:

  - |

    mmc@d00d4000 {

      compatible = "marvell,orion-sdio";

      reg = <0xd00d4000 0x200>;

      interrupts = <54>;

      clocks = <&gateclk 17>;

    };

Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt

deleted100644 → 0
+0 −173
Original line number Diff line number Diff line 
Marvell Xenon SDHCI Controller device tree bindings

This file documents differences between the core mmc properties

described by mmc.txt and the properties used by the Xenon implementation.



Multiple SDHCs might be put into a single Xenon IP, to save size and cost.

Each SDHC is independent and owns independent resources, such as register sets,

clock and PHY.

Each SDHC should have an independent device tree node.



Required Properties:

- compatible: should be one of the following

  - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.

  Must provide a second register area and marvell,pad-type.

  - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.

  - "marvell,armada-ap807-sdhci": For controllers on Armada AP807.

  - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.



- clocks:

  Array of clocks required for SDHC.

  Require at least input clock for Xenon IP core. For Armada AP806 and

  CP110, the AXI clock is also mandatory.



- clock-names:

  Array of names corresponding to clocks property.

  The input clock for Xenon IP core should be named as "core".

  The input clock for the AXI bus must be named as "axi".



- reg:

  * For "marvell,armada-3700-sdhci", two register areas.

    The first one for Xenon IP register. The second one for the Armada 3700 SoC

    PHY PAD Voltage Control register.

    Please follow the examples with compatible "marvell,armada-3700-sdhci"

    in below.

    Please also check property marvell,pad-type in below.



  * For other compatible strings, one register area for Xenon IP.



Optional Properties:

- marvell,xenon-sdhc-id:

  Indicate the corresponding bit index of current SDHC in

  SDHC System Operation Control Register Bit[7:0].

  Set/clear the corresponding bit to enable/disable current SDHC.

  If Xenon IP contains only one SDHC, this property is optional.



- marvell,xenon-phy-type:

  Xenon support multiple types of PHYs.

  To select eMMC 5.1 PHY, set:

  marvell,xenon-phy-type = "emmc 5.1 phy"

  eMMC 5.1 PHY is the default choice if this property is not provided.

  To select eMMC 5.0 PHY, set:

  marvell,xenon-phy-type = "emmc 5.0 phy"



  All those types of PHYs can support eMMC, SD and SDIO.

  Please note that this property only presents the type of PHY.

  It doesn't stand for the entire SDHC type or property.

  For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only

  supports eMMC 5.1.



- marvell,xenon-phy-znr:

  Set PHY ZNR value.

  Only available for eMMC PHY.

  Valid range = [0:0x1F].

  ZNR is set as 0xF by default if this property is not provided.



- marvell,xenon-phy-zpr:

  Set PHY ZPR value.

  Only available for eMMC PHY.

  Valid range = [0:0x1F].

  ZPR is set as 0xF by default if this property is not provided.



- marvell,xenon-phy-nr-success-tun:

  Set the number of required consecutive successful sampling points

  used to identify a valid sampling window, in tuning process.

  Valid range = [1:7].

  Set as 0x4 by default if this property is not provided.



- marvell,xenon-phy-tun-step-divider:

  Set the divider for calculating TUN_STEP.

  Set as 64 by default if this property is not provided.



- marvell,xenon-phy-slow-mode:

  If this property is selected, transfers will bypass PHY.

  Only available when bus frequency lower than 55MHz in SDR mode.

  Disabled by default. Please only try this property if timing issues

  always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,

  SD Default Speed and HS mode and eMMC legacy speed mode.



- marvell,xenon-tun-count:

  Xenon SDHC SoC usually doesn't provide re-tuning counter in

  Capabilities Register 3 Bit[11:8].

  This property provides the re-tuning counter.

  If this property is not set, default re-tuning counter will

  be set as 0x9 in driver.



- marvell,pad-type:

  Type of Armada 3700 SoC PHY PAD Voltage Controller register.

  Only valid when "marvell,armada-3700-sdhci" is selected.

  Two types: "sd" and "fixed-1-8v".

  If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is

  switched to 1.8V when later in higher speed mode.

  If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC.

  Please follow the examples with compatible "marvell,armada-3700-sdhci"

  in below.



Example:

- For eMMC:



	sdhci@aa0000 {

		compatible = "marvell,armada-ap806-sdhci";

		reg = <0xaa0000 0x1000>;

		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>

		clocks = <&emmc_clk>,<&axi_clk>;

		clock-names = "core", "axi";

		bus-width = <4>;

		marvell,xenon-phy-slow-mode;

		marvell,xenon-tun-count = <11>;

		non-removable;

		no-sd;

		no-sdio;



		/* Vmmc and Vqmmc are both fixed */

	};



- For SD/SDIO:



	sdhci@ab0000 {

		compatible = "marvell,armada-cp110-sdhci";

		reg = <0xab0000 0x1000>;

		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>

		vqmmc-supply = <&sd_vqmmc_regulator>;

		vmmc-supply = <&sd_vmmc_regulator>;

		clocks = <&sdclk>, <&axi_clk>;

		clock-names = "core", "axi";

		bus-width = <4>;

		marvell,xenon-tun-count = <9>;

	};



- For eMMC with compatible "marvell,armada-3700-sdhci":



	sdhci@aa0000 {

		compatible = "marvell,armada-3700-sdhci";

		reg = <0xaa0000 0x1000>,

		      <phy_addr 0x4>;

		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>

		clocks = <&emmcclk>;

		clock-names = "core";

		bus-width = <8>;

		mmc-ddr-1_8v;

		mmc-hs400-1_8v;

		non-removable;

		no-sd;

		no-sdio;



		/* Vmmc and Vqmmc are both fixed */



		marvell,pad-type = "fixed-1-8v";

	};



- For SD/SDIO with compatible "marvell,armada-3700-sdhci":



	sdhci@ab0000 {

		compatible = "marvell,armada-3700-sdhci";

		reg = <0xab0000 0x1000>,

		      <phy_addr 0x4>;

		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>

		vqmmc-supply = <&sd_regulator>;

		/* Vmmc is fixed */

		clocks = <&sdclk>;

		clock-names = "core";

		bus-width = <4>;



		marvell,pad-type = "sd";

	};