Commit 6385cbe9 authored Jan 06, 2020 by Roger Quadros Committed by Kishon Vijay Abraham I Jan 14, 2020

dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO



This is an optional GPIO, if specified will be used to
swap lane 0 and lane 1 based on GPIO status. This is required
to achieve plug flip support for USB Type-C.

Type-C companions typically need some time after the cable is
plugged before and before they reflect the correct status of
Type-C plug orientation on the DIR line.

Type-C Spec specifies CC attachment debounce time (tCCDebounce)
of 100 ms (min) to 200 ms (max).

Allow the DT node to specify the time (in ms) that we need
to wait before sampling the DIR line.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Cc: Rob Herring <robh@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

parent 7904e15b

Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

+17 −0

Original line number	Diff line number	Diff line
		@@ -50,6 +50,23 @@ properties:
		assigned-clock-parents:
		maxItems: 2

		typec-dir-gpios:
		maxItems: 1
		description:
		GPIO to signal Type-C cable orientation for lane swap.
		If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
		achieve the funtionality of an external type-C plug flip mux.

		typec-dir-debounce-ms:
		minimum: 100
		maximum: 1000
		default: 100
		description:
		Number of milliseconds to wait before sampling typec-dir-gpio.
		If not specified, the default debounce of 100ms will be used.
		Type-C spec states minimum CC pin debounce of 100 ms and maximum
		of 200 ms. However, some solutions might need more than 200 ms.

		patternProperties:
		"^pll[0\|1]-refclk$":
		type: object