Commit 6384d44b authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher
Browse files

drm/amdgpu/pm: add smu v13.0.4 driver SMU if headers 



Add smu v13.0.4 driver SMU interface headers.

v2: squash in the header updates (Alex)

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarTim Huang <Tim.Huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7bd3114b

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_4.h

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/*

 * Copyright 2022 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __SMU13_DRIVER_IF_V13_0_4_H__

#define __SMU13_DRIVER_IF_V13_0_4_H__



// *** IMPORTANT ***

// SMU TEAM: Always increment the interface version if

// any structure is changed in this file

#define PMFW_DRIVER_IF_VERSION 4



typedef struct {

  int32_t value;

  uint32_t numFractionalBits;

} FloatInIntFormat_t;



typedef enum {

  DSPCLK_DCFCLK = 0,

  DSPCLK_DISPCLK,

  DSPCLK_PIXCLK,

  DSPCLK_PHYCLK,

  DSPCLK_COUNT,

} DSPCLK_e;



typedef struct {

  uint16_t Freq; // in MHz

  uint16_t Vid;  // min voltage in SVI3 VID

} DisplayClockTable_t;



typedef struct {

  uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)

  uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)

  uint16_t MinMclk;

  uint16_t MaxMclk;



  uint8_t  WmSetting;

  uint8_t  WmType;  // Used for normal pstate change or memory retraining

  uint8_t  Padding[2];

} WatermarkRowGeneric_t;



#define NUM_WM_RANGES 4

#define WM_PSTATE_CHG 0

#define WM_RETRAINING 1



typedef enum {

  WM_SOCCLK = 0,

  WM_DCFCLK,

  WM_COUNT,

} WM_CLOCK_e;



typedef struct {

  // Watermarks

  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];



  uint32_t MmHubPadding[7]; // SMU internal use

} Watermarks_t;



typedef enum {

  CUSTOM_DPM_SETTING_GFXCLK,

  CUSTOM_DPM_SETTING_CCLK,

  CUSTOM_DPM_SETTING_FCLK_CCX,

  CUSTOM_DPM_SETTING_FCLK_GFX,

  CUSTOM_DPM_SETTING_FCLK_STALLS,

  CUSTOM_DPM_SETTING_LCLK,

  CUSTOM_DPM_SETTING_COUNT,

} CUSTOM_DPM_SETTING_e;



typedef struct {

  uint8_t             ActiveHystLimit;

  uint8_t             IdleHystLimit;

  uint8_t             FPS;

  uint8_t             MinActiveFreqType;

  FloatInIntFormat_t  MinActiveFreq;

  FloatInIntFormat_t  PD_Data_limit;

  FloatInIntFormat_t  PD_Data_time_constant;

  FloatInIntFormat_t  PD_Data_error_coeff;

  FloatInIntFormat_t  PD_Data_error_rate_coeff;

} DpmActivityMonitorCoeffExt_t;



typedef struct {

  DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];

} CustomDpmSettings_t;



#define NUM_DCFCLK_DPM_LEVELS   8

#define NUM_DISPCLK_DPM_LEVELS  8

#define NUM_DPPCLK_DPM_LEVELS   8

#define NUM_SOCCLK_DPM_LEVELS   8

#define NUM_VCN_DPM_LEVELS      8

#define NUM_SOC_VOLTAGE_LEVELS  8

#define NUM_DF_PSTATE_LEVELS    4



typedef struct {

  uint32_t FClk;

  uint32_t MemClk;

  uint32_t Voltage;

  uint8_t  WckRatio;

  uint8_t  Spare[3];

} DfPstateTable_t;



//Freq in MHz

//Voltage in milli volts with 2 fractional bits

typedef struct {

  uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

  uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

  uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

  uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

  uint32_t VClocks[NUM_VCN_DPM_LEVELS];

  uint32_t DClocks[NUM_VCN_DPM_LEVELS];

  uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

  DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];



  uint8_t  NumDcfClkLevelsEnabled;

  uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

  uint8_t  NumSocClkLevelsEnabled;

  uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk

  uint8_t  NumDfPstatesEnabled;

  uint8_t  spare[3];



  uint32_t MinGfxClk;

  uint32_t MaxGfxClk;

} DpmClocks_t;





// Throttler Status Bitmask

#define THROTTLER_STATUS_BIT_SPL            0

#define THROTTLER_STATUS_BIT_FPPT           1

#define THROTTLER_STATUS_BIT_SPPT           2

#define THROTTLER_STATUS_BIT_SPPT_APU       3

#define THROTTLER_STATUS_BIT_THM_CORE       4

#define THROTTLER_STATUS_BIT_THM_GFX        5

#define THROTTLER_STATUS_BIT_THM_SOC        6

#define THROTTLER_STATUS_BIT_TDC_VDD        7

#define THROTTLER_STATUS_BIT_TDC_SOC        8

#define THROTTLER_STATUS_BIT_PROCHOT_CPU    9

#define THROTTLER_STATUS_BIT_PROCHOT_GFX   10

#define THROTTLER_STATUS_BIT_EDC_CPU       11

#define THROTTLER_STATUS_BIT_EDC_GFX       12



typedef struct {

  uint16_t GfxclkFrequency;             //[MHz]

  uint16_t SocclkFrequency;             //[MHz]

  uint16_t VclkFrequency;               //[MHz]

  uint16_t DclkFrequency;               //[MHz]

  uint16_t MemclkFrequency;             //[MHz]

  uint16_t spare;                       //[centi]

  uint16_t UvdActivity;                 //[centi]

  uint16_t GfxActivity;                 //[centi]



  uint16_t Voltage[2];                  //[mV] indices: VDDCR_VDD, VDDCR_SOC

  uint16_t Current[2];                  //[mA] indices: VDDCR_VDD, VDDCR_SOC

  uint16_t Power[2];                    //[mW] indices: VDDCR_VDD, VDDCR_SOC



  //3rd party tools in Windows need this info in the case of APUs

  uint16_t CoreFrequency[8];            //[MHz]

  uint16_t CorePower[8];                //[mW]

  uint16_t CoreTemperature[8];          //[centi-Celsius]

  uint16_t L3Frequency;                 //[MHz]

  uint16_t L3Temperature;               //[centi-Celsius]



  uint16_t GfxTemperature;              //[centi-Celsius]

  uint16_t SocTemperature;              //[centi-Celsius]

  uint16_t ThrottlerStatus;



  uint16_t CurrentSocketPower;          //[mW]

  uint16_t StapmOpnLimit;               //[W]

  uint16_t StapmCurrentLimit;           //[W]

  uint32_t ApuPower;                    //[mW]

  uint32_t dGpuPower;                   //[mW]



  uint16_t VddTdcValue;                 //[mA]

  uint16_t SocTdcValue;                 //[mA]

  uint16_t VddEdcValue;                 //[mA]

  uint16_t SocEdcValue;                 //[mA]



  uint16_t InfrastructureCpuMaxFreq;    //[MHz]

  uint16_t InfrastructureGfxMaxFreq;    //[MHz]



  uint16_t SkinTemp;

  uint16_t DeviceState;

} SmuMetrics_t;



typedef struct {

  uint16_t StapmMaxPlatformLimit;            //[W]

  uint16_t StapmMinPlatformLimit;            //[W]

  uint16_t FastPptMaxPlatformLimit;          //[W]

  uint16_t FastPptMinPlatformLimit;          //[W]

  uint16_t SlowPptMaxPlatformLimit;          //[W]

  uint16_t SlowPptMinPlatformLimit;          //[W]

  uint16_t SlowPptApuMaxPlatformLimit;       //[W]

  uint16_t SlowPptApuMinPlatformLimit;       //[W]

} PmfInfo_t;



//ISP tile definitions

typedef enum {

  TILE_ISPX = 0, // ISPX

  TILE_ISPM,     // ISPM

  TILE_ISPC,  // ISPCORE

  TILE_ISPPRE,   // ISPPRE

  TILE_ISPPOST0,  // ISPPOST0,

  TILE_ISPPOST1,  // ISPPOST1

  TILE_MAX

} TILE_NUM_e;



// Tile Selection (Based on arguments)

#define TILE_SEL_ISPX       (1<<(TILE_ISPX))

#define TILE_SEL_ISPM       (1<<(TILE_ISPM))

#define TILE_SEL_ISPC       (1<<(TILE_ISPC))

#define TILE_SEL_ISPPRE     (1<<(TILE_ISPPRE))

#define TILE_SEL_ISPPOST0   (1<<(TILE_ISPPOST0))

#define TILE_SEL_ISPPOST1   (1<<(TILE_ISPPOST1))





// Mask for ISP tiles in PGFSM PWR Status Registers

//Bit[1:0] maps to ISPX, (ISPX)

//Bit[3:2] maps to ISPM, (ISPM)

//Bit[5:4] maps to ISPCORE, (ISPCORE)

//Bit[7:6] maps to ISPPRE, (ISPPRE)

//Bit[9:8] maps to POST, (ISPPOST

#define TILE_ISPX_MASK      ((1<<0) | (1<<1))

#define TILE_ISPM_MASK      ((1<<2) | (1<<3))

#define TILE_ISPC_MASK      ((1<<4) | (1<<5))

#define TILE_ISPPRE_MASK    ((1<<6) | (1<<7))

#define TILE_ISPPOST0_MASK  ((1<<8) | (1<<9))

#define TILE_ISPPOST1_MASK  ((1<<10) | (1<<11))





// Workload bits

#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0

#define WORKLOAD_PPLIB_VIDEO_BIT          2

#define WORKLOAD_PPLIB_VR_BIT             3

#define WORKLOAD_PPLIB_COMPUTE_BIT        4

#define WORKLOAD_PPLIB_CUSTOM_BIT         5

#define WORKLOAD_PPLIB_COUNT              6



#define TABLE_BIOS_IF               0 // Called by BIOS

#define TABLE_WATERMARKS            1 // Called by DAL through VBIOS

#define TABLE_CUSTOM_DPM            2 // Called by Driver

#define TABLE_SPARE1                3

#define TABLE_DPMCLOCKS             4 // Called by Driver and VBIOS

#define TABLE_MOMENTARY_PM          5 // Called by Tools

#define TABLE_MODERN_STDBY          6 // Called by Tools for Modern Standby Log

#define TABLE_SMU_METRICS           7 // Called by Driver and PMF

#define TABLE_INFRASTRUCTURE_LIMITS 8 // Called by PMF

#define TABLE_COUNT                 9



#endif

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_pmfw.h

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/*

 * Copyright 2022 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __SMU_V13_0_4_PMFW_H__

#define __SMU_V13_0_4_PMFW_H__



#include "smu13_driver_if_v13_0_4.h"



#pragma pack(push, 1)



#define ENABLE_DEBUG_FEATURES



// Firmware features

// Feature Control Defines

#define FEATURE_CCLK_DPM_BIT                 0

#define FEATURE_FAN_CONTROLLER_BIT           1

#define FEATURE_DATA_CALCULATION_BIT         2

#define FEATURE_PPT_BIT                      3

#define FEATURE_TDC_BIT                      4

#define FEATURE_THERMAL_BIT                  5

#define FEATURE_FIT_BIT                      6

#define FEATURE_EDC_BIT                      7

#define FEATURE_PLL_POWER_DOWN_BIT           8

#define FEATURE_VDDOFF_BIT                   9

#define FEATURE_VCN_DPM_BIT                 10

#define FEATURE_CSTATE_BOOST_BIT            11

#define FEATURE_FCLK_DPM_BIT                12

#define FEATURE_SOCCLK_DPM_BIT              13

#define FEATURE_MP0CLK_DPM_BIT              14

#define FEATURE_LCLK_DPM_BIT                15

#define FEATURE_SHUBCLK_DPM_BIT             16

#define FEATURE_DCFCLK_DPM_BIT              17

#define FEATURE_ISP_DPM_BIT                 18

#define FEATURE_IPU_DPM_BIT                 19

#define FEATURE_GFX_DPM_BIT                 20

#define FEATURE_DS_GFXCLK_BIT               21

#define FEATURE_DS_SOCCLK_BIT               22

#define FEATURE_DS_LCLK_BIT                 23

#define FEATURE_DS_DCFCLK_BIT               24

#define FEATURE_DS_SHUBCLK_BIT              25

#define FEATURE_GFX_TEMP_VMIN_BIT           26

#define FEATURE_ZSTATES_BIT                 27

#define FEATURE_WHISPER_MODE_BIT            28

#define FEATURE_DS_FCLK_BIT                 29

#define FEATURE_DS_SMNCLK_BIT               30

#define FEATURE_DS_MP1CLK_BIT               31

#define FEATURE_DS_MP0CLK_BIT               32

#define FEATURE_SMU_LOW_POWER_BIT           33

#define FEATURE_FUSE_PG_BIT                 34

#define FEATURE_GFX_DEM_BIT                 35

#define FEATURE_PSI_BIT                     36

#define FEATURE_PROCHOT_BIT                 37

#define FEATURE_CPUOFF_BIT                  38

#define FEATURE_STAPM_BIT                   39

#define FEATURE_S0I3_BIT                    40

#define FEATURE_DF_LIGHT_CSTATE             41   // shift the order or DFCstate annd DF light Cstate

#define FEATURE_PERF_LIMIT_BIT              42

#define FEATURE_CORE_DLDO_BIT               43

//#define FEATURE_RSMU_LOW_POWER_BIT          44 //temp removal for DVO

#define FEATURE_DVO_BIT                     44

#define FEATURE_DS_VCN_BIT                  45

#define FEATURE_CPPC_BIT                    46

#define FEATURE_CPPC_PREFERRED_CORES        47

#define FEATURE_DF_CSTATES_BIT              48

#define FEATURE_FASTBYPASS_CLDO_BIT         49

#define FEATURE_ATHUB_PG_BIT                50

#define FEATURE_VDDOFF_ECO_BIT              51

#define FEATURE_ZSTATES_ECO_BIT             52

#define FEATURE_CC6_BIT                     53

#define FEATURE_DS_UMCCLK_BIT               54

#define FEATURE_DS_ISPCLK_BIT               55

#define FEATURE_DS_HSPCLK_BIT               56

#define FEATURE_MPCCX_WHISPER_MODE_BIT      57

#define FEATURE_DS_IPUCLK_BIT               58

#define NUM_FEATURES                        59



typedef struct {

  // MP1_EXT_SCRATCH0

  uint32_t DpmHandlerID         : 8;

  uint32_t ActivityMonitorID    : 8;

  uint32_t DpmTimerID           : 8;

  uint32_t DpmHubID             : 4;

  uint32_t DpmHubTask           : 4;

  // MP1_EXT_SCRATCH1

  uint32_t GfxoffStatus         : 8;

  uint32_t GfxStatus            : 2;

  uint32_t CpuOff               : 2;

  uint32_t VddOff               : 1;

  uint32_t InUlv                : 1;

  uint32_t InWhisperMode        : 1;

  uint32_t spare0               : 1;

  uint32_t ZstateStatus         : 4;

  uint32_t spare1               : 4;

  uint32_t DstateFun            : 4;

  uint32_t DstateDev            : 4;

  // MP1_EXT_SCRATCH2

  uint32_t P2JobHandler         :32;

  // MP1_EXT_SCRATCH3

  uint32_t PostCode             :32;

  // MP1_EXT_SCRATCH4

  uint32_t MsgPortBusy          :15;

  uint32_t RsmuPmiP1Pending     : 1;

  uint32_t RsmuPmiP2PendingCnt  : 8;

  uint32_t DfCstateExitPending  : 1;

  uint32_t Pc6EntryPending      : 1;

  uint32_t Pc6ExitPending       : 1;

  uint32_t WarmResetPending     : 1;

  uint32_t Mp0ClkPending        : 1;

  uint32_t spare2               : 3;

  // MP1_EXT_SCRATCH5

  uint32_t IdleMask             :32;

} FwStatus_t;





#pragma pack(pop)



#endif

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_4_ppsmc.h

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/*

 * Copyright 2022 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __SMU_V13_0_4_PPSMC_H__

#define __SMU_V13_0_4_PPSMC_H__



/*! @mainpage PMFW-PPS (PPLib) Message Interface

  This documentation contains the subsections:\n\n

  @ref ResponseCodes\n

  @ref definitions\n

  @ref enums\n

*/



/** @def PPS_PMFW_IF_VER

* PPS (PPLib) to PMFW IF version 1.0

*/

#define PPS_PMFW_IF_VER "1.0" ///< Major.Minor



/** @defgroup ResponseCodes PMFW Response Codes

*  @{

*/

// SMU Response Codes:

#define PPSMC_Result_OK                    0x1  ///< Message Response OK

#define PPSMC_Result_Failed                0xFF ///< Message Response Failed

#define PPSMC_Result_UnknownCmd            0xFE ///< Message Response Unknown Command

#define PPSMC_Result_CmdRejectedPrereq     0xFD ///< Message Response Command Failed Prerequisite

#define PPSMC_Result_CmdRejectedBusy       0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message

/** @}*/



/** @defgroup definitions Message definitions

*  @{

*/

// Message Definitions:

#define PPSMC_MSG_TestMessage                   0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team

#define PPSMC_MSG_GetPmfwVersion                0x02 ///< Get PMFW version

#define PPSMC_MSG_GetDriverIfVersion            0x03 ///< Get PMFW_DRIVER_IF version

#define PPSMC_MSG_EnableGfxOff                  0x04 ///< Enable GFXOFF

#define PPSMC_MSG_DisableGfxOff                 0x05 ///< Disable GFXOFF

#define PPSMC_MSG_PowerDownVcn                  0x06 ///< Power down VCN

#define PPSMC_MSG_PowerUpVcn                    0x07 ///< Power up VCN; VCN is power gated by default

#define PPSMC_MSG_SetHardMinVcn                 0x08 ///< For wireless display

#define PPSMC_MSG_SetSoftMinGfxclk              0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz

#define PPSMC_MSG_ActiveProcessNotify           0x0A ///< Needs update

#define PPSMC_MSG_ForcePowerDownGfx             0x0B ///< Force power down GFX, i.e. enter GFXOFF

#define PPSMC_MSG_PrepareMp1ForUnload           0x0C ///< Prepare PMFW for GFX driver unload

#define PPSMC_MSG_SetDriverDramAddrHigh         0x0D ///< Set high 32 bits of DRAM address for Driver table transfer

#define PPSMC_MSG_SetDriverDramAddrLow          0x0E ///< Set low 32 bits of DRAM address for Driver table transfer

#define PPSMC_MSG_TransferTableSmu2Dram         0x0F ///< Transfer driver interface table from PMFW SRAM to DRAM

#define PPSMC_MSG_TransferTableDram2Smu         0x10 ///< Transfer driver interface table from DRAM to PMFW SRAM

#define PPSMC_MSG_GfxDeviceDriverReset          0x11 ///< Request GFX mode 2 reset

#define PPSMC_MSG_GetEnabledSmuFeatures         0x12 ///< Get enabled features in PMFW

#define PPSMC_MSG_SetHardMinSocclkByFreq        0x13 ///< Set hard min for SOC CLK

#define PPSMC_MSG_SetSoftMinFclk                0x14 ///< Set hard min for FCLK

#define PPSMC_MSG_SetSoftMinVcn                 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)





#define PPSMC_MSG_EnableGfxImu                  0x16 ///< Needs update



#define PPSMC_MSG_GetGfxclkFrequency            0x17 ///< Get GFX clock frequency

#define PPSMC_MSG_GetFclkFrequency              0x18 ///< Get FCLK frequency

#define PPSMC_MSG_AllowGfxOff                   0x19 ///< Inform PMFW of allowing GFXOFF entry

#define PPSMC_MSG_DisallowGfxOff                0x1A ///< Inform PMFW of disallowing GFXOFF entry

#define PPSMC_MSG_SetSoftMaxGfxClk              0x1B ///< Set soft max for GFX CLK

#define PPSMC_MSG_SetHardMinGfxClk              0x1C ///< Set hard min for GFX CLK



#define PPSMC_MSG_SetSoftMaxSocclkByFreq        0x1D ///< Set soft max for SOC CLK

#define PPSMC_MSG_SetSoftMaxFclkByFreq          0x1E ///< Set soft max for FCLK

#define PPSMC_MSG_SetSoftMaxVcn                 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK)

#define PPSMC_MSG_SetPowerLimitPercentage       0x20 ///< Set power limit percentage

#define PPSMC_MSG_PowerDownJpeg                 0x21 ///< Power down Jpeg

#define PPSMC_MSG_PowerUpJpeg                   0x22 ///< Power up Jpeg; VCN is power gated by default



#define PPSMC_MSG_SetHardMinFclkByFreq          0x23 ///< Set hard min for FCLK

#define PPSMC_MSG_SetSoftMinSocclkByFreq        0x24 ///< Set soft min for SOC CLK

#define PPSMC_MSG_AllowZstates                  0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity

#define PPSMC_MSG_Reserved                      0x26 ///< Not used

#define PPSMC_MSG_Reserved1                     0x27 ///< Not used, previously PPSMC_MSG_RequestActiveWgp

#define PPSMC_MSG_Reserved2                     0x28 ///< Not used, previously PPSMC_MSG_QueryActiveWgp

#define PPSMC_MSG_PowerDownIspByTile            0x29 ///< ISP is power gated by default

#define PPSMC_MSG_PowerUpIspByTile              0x2A ///< This message is used to power up ISP tiles and enable the ISP DPM

#define PPSMC_MSG_SetHardMinIspiclkByFreq       0x2B ///< Set HardMin by frequency for ISPICLK

#define PPSMC_MSG_SetHardMinIspxclkByFreq       0x2C ///< Set HardMin by frequency for ISPXCLK

#define PPSMC_MSG_PowerDownUmsch                0x2D ///< Power down VCN.UMSCH (aka VSCH) scheduler

#define PPSMC_MSG_PowerUpUmsch                  0x2E ///< Power up VCN.UMSCH (aka VSCH) scheduler

#define PPSMC_Message_IspStutterOn_MmhubPgDis   0x2F ///< ISP StutterOn mmHub PgDis

#define PPSMC_Message_IspStutterOff_MmhubPgEn   0x30 ///< ISP StufferOff mmHub PgEn



#define PPSMC_Message_Count                     0x31 ///< Total number of PPSMC messages

/** @}*/



/**

* @defgroup enums Enum Definitions

*  @{

*/



/** @enum Mode_Reset_e

* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset

*/

//argument for PPSMC_MSG_GfxDeviceDriverReset

typedef enum {

  MODE1_RESET = 1,  ///< Mode reset type 1

  MODE2_RESET = 2   ///< Mode reset type 2

} Mode_Reset_e;



/** @}*/



/** @enum ZStates_e

* Zstate types, argument for PPSMC_MSG_AllowZstates

*/

//Argument for PPSMC_MSG_AllowZstates

typedef enum  {

  DISALLOW_ZSTATES = 0, ///< Disallow Zstates

  ALLOW_ZSTATES_Z8 = 8, ///< Allows Z8 only

  ALLOW_ZSTATES_Z9 = 9, ///< Allows Z9 and Z8

} ZStates_e;



/** @}*/

#endif