Commit 6361b7de authored by Xingyu Wu's avatar Xingyu Wu Committed by Conor Dooley
Browse files

riscv: dts: starfive: jh7110: Add watchdog node 



Add the watchdog node for the Starfive JH7110 SoC.

Signed-off-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: default avatarWalker Chen <walker.chen@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 435ac3fb

arch/riscv/boot/dts/starfive/jh7110.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -469,6 +469,16 @@ 
			#gpio-cells = <2>;

		};



		watchdog@13070000 {

			compatible = "starfive,jh7110-wdt";

			reg = <0x0 0x13070000 0x0 0x10000>;

			clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,

				 <&syscrg JH7110_SYSCLK_WDT_CORE>;

			clock-names = "apb", "core";

			resets = <&syscrg JH7110_SYSRST_WDT_APB>,

				 <&syscrg JH7110_SYSRST_WDT_CORE>;

		};



		aoncrg: clock-controller@17000000 {

			compatible = "starfive,jh7110-aoncrg";

			reg = <0x0 0x17000000 0x0 0x10000>;