Commit 6349c738 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: For ODM seamless transition require AUTO mode 



[Why & How]
ODM seamless transitions require DIV_MODE_AUTO. However,
DIV_MODE_AUTO only works when all the horizontal timing params
are divisible by the ODM combine factor. Therefore, disable the
ODM 2:1 policy when the horizontal timing params are not divisible
by 2.

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cc67aae1

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+22 −0
Original line number Diff line number Diff line
@@ -3645,3 +3645,25 @@ const struct link_hwss *get_link_hwss(const struct dc_link *link, 
	else

		return get_virtual_link_hwss();

}



bool is_h_timing_divisible_by_2(struct dc_stream_state *stream)

{

	bool divisible = false;

	uint16_t h_blank_start = 0;

	uint16_t h_blank_end = 0;



	if (stream) {

		h_blank_start = stream->timing.h_total - stream->timing.h_front_porch;

		h_blank_end = h_blank_start - stream->timing.h_addressable;



		/* HTOTAL, Hblank start/end, and Hsync start/end all must be

		 * divisible by 2 in order for the horizontal timing params

		 * to be considered divisible by 2. Hsync start is always 0.

		 */

		divisible = (stream->timing.h_total % 2 == 0) &&

				(h_blank_start % 2 == 0) &&

				(h_blank_end % 2 == 0) &&

				(stream->timing.h_sync_width % 2 == 0);

	}

	return divisible;

}
 
 No newline at end of file

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+2 −1
Original line number Diff line number Diff line
@@ -1871,7 +1871,8 @@ int dcn32_populate_dml_pipes_from_context( 
		timing = &pipe->stream->timing;



		pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;

		if (context->stream_count == 1 && !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal)) {

		if (context->stream_count == 1 && !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) &&

				is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream)) {

			if (dc->debug.enable_single_display_2to1_odm_policy) {

				if (!((plane_count > 2) && pipe->top_pipe))

					pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;

drivers/gpu/drm/amd/display/dc/inc/resource.h

+2 −0
Original line number Diff line number Diff line
@@ -224,4 +224,6 @@ uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter tr 
const struct link_hwss *get_link_hwss(const struct dc_link *link,

		const struct link_resource *link_res);



bool is_h_timing_divisible_by_2(struct dc_stream_state *stream);



#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */