Commit 6335ae3f authored by wenglianfa's avatar wenglianfa Committed by Chengchang Tang
Browse files

RDMA/hns: Fix the valid QP bank set to improve performance 

driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IB2HJE



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QP banks 0, 1, 4, and 5 use one HW FIFO, while QP banks 2, 3, 6,
and 7 use another. Currently, if HNS_ROCE_CAP_FLAG_LIMIT_BANK is
set, only QP banks 0, 1, 4, and 5 are used, resulting in a single
HW FIFO being utilized. Instead, it is proposed to use QP banks 0,
1, 6, and 7 to leverage different FIFOs and improve performance.

Fixes: 1c167016 ("RDMA/hns: Fix RoCEE hang when multiple QP banks use EXT_SGE")
Signed-off-by: default avatarwenglianfa <wenglianfa@huawei.com>
Signed-off-by: default avatarXinghai Cen <cenxinghai@h-partners.com>
parent 3faacfa7

drivers/infiniband/hw/hns/hns_roce_device.h

+2 −2
Original line number Diff line number Diff line
@@ -113,9 +113,9 @@ 
#define CQ_BANKID_MASK GENMASK(1, 0)



#define VALID_CQ_BANK_MASK_DEFAULT 0xF

#define VALID_CQ_BANK_MASK_LIMIT 0x5

#define VALID_CQ_BANK_MASK_LIMIT 0x9



#define QP_HARDEN_MASK GENMASK(1, 0)

#define VALID_EXT_SGE_QP_BANK_MASK_LIMIT 0x41



#define HNS_ROCE_MAX_CQ_COUNT 0xFFFF

#define HNS_ROCE_MAX_CQ_PERIOD 0xFFFF

drivers/infiniband/hw/hns/hns_roce_qp.c

+2 −1
Original line number Diff line number Diff line
@@ -244,7 +244,8 @@ static u8 select_qp_bankid(struct hns_roce_dev *hr_dev, 
			continue;



		if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_LIMIT_BANK) &&

		    use_ext_sge(init_attr) && (QP_HARDEN_MASK & i))

		    use_ext_sge(init_attr) &&

		    !(VALID_EXT_SGE_QP_BANK_MASK_LIMIT & BIT(i)))

			continue;



		valid_qp_bank_mask |= BIT(i);