Commit 62f0576c authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: fix dcn315 memory channel count and width read 



[Why & How]
Correctly set ddr5 channel width to 8 bytes

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 22c42b0e

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c

+1 −2
Original line number Diff line number Diff line
@@ -561,8 +561,7 @@ static void dcn315_clk_mgr_helper_populate_bw_params( 
	ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);

	bw_params->vram_type = bios_info->memory_type;

	bw_params->num_channels = bios_info->ma_channel_number;

	if (!bw_params->num_channels)

		bw_params->num_channels = 2;

	bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;



	for (i = 0; i < WM_SET_COUNT; i++) {

		bw_params->wm_table.entries[i].wm_inst = i;

drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c

+6 −1
Original line number Diff line number Diff line
@@ -291,6 +291,7 @@ static struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = { 
	.do_urgent_latency_adjustment = false,

	.urgent_latency_adjustment_fabric_clock_component_us = 0,

	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,

	.num_chans = 4,

};



struct _vcs_dpi_ip_params_st dcn3_16_ip = {
@@ -688,7 +689,11 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 


	dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;

	dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count;



	if (bw_params->num_channels > 0)

		dcn3_15_soc.num_chans = bw_params->num_channels;

	if (bw_params->dram_channel_width_bytes > 0)

		dcn3_15_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes;



	ASSERT(clk_table->num_entries);